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LAN9117 데이터시트(HTML) 42 Page - Microchip Technology

부품명 LAN9117
상세내용  High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
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제조사  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
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LAN9117 데이터시트(HTML) 42 Page - Microchip Technology

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LAN9117
DS00002267A-page 42
 2005-2016 Microchip Technology Inc.
3.13.4
TX STATUS FORMAT
TX status is passed to the host CPU through a separate FIFO mechanism. A status word is returned for each packet
transmitted. Data transmission is suspended if the TX status FIFO becomes full. Data transmission will resume when
the host reads the TX status and there is room in the FIFO for more “TX Status” data.
The host can optionally choose to not read the TX status. The host can optionally ignore the TX status by setting the
“TX Status Discard Allow Overrun Enable” (TXSAO) bit in the TX Configuration Register (TX_CFG). If this option is cho-
sen TX status will not be written to the FIFO. Setting this bit high allows the transmitter to continue operation with a full
TX status FIFO. In this mode the status information is still available in the TX status FIFO, and TX status interrupts still
function. In the case of an overrun, the TXSUSED counter will stay at zero and no further TX status will be written to the
TX status FIFO until the host frees space by reading TX status. If TXSAO is enabled, a TXE error will not be generated
if the TX status FIFO overruns. In this mode the host is responsible for re-synchronizing TX status in the case of an
overrun.
3.13.5
CALCULATING ACTUAL TX DATA FIFO USAGE
The following rules are used to calculate the actual TX data FIFO space consumed by a TX Packet:
• TX command 'A' is stored in the TX data FIFO for every TX buffer
• TX command 'B' is written into the TX data FIFO when the First Segment (FS) bit is set in TX command 'A'
• Any DWORD-long data added as part of the “Data Start Offset” is removed from each buffer before the data is
written to the TX data FIFO. Any data that is less than 1 DWORD is passed to the TX data FIFO.
• Payload from each buffer within a Packet is written into the TX data FIFO.
• Any DWORD-long data added as part of the End Padding is removed from each buffer before the data is written to
the TX data FIFO. Any end padding that is less than 1 DWORD is passed to the TX data FIFO.
Bits
Description
31:16
Packet TAG. Unique identifier written by the host into the Packet Tag field of the TX command ‘B’
word. This field can be used by the host to correlate TX status words with the associated TX packets.
15
Error Status (ES). When set, this bit indicates that the Ethernet controller has reported an error. This
bit is the logical OR of bits 11, 10, 9, 8, 2, 1 in this status word.
14:12
Reserved. These bits are reserved. Always write zeros to this field to provide future compatibility.
11
Loss of Carrier. When set, this bit indicates the loss of carrier during transmission.
10
No Carrier. When set, this bit indicates that the carrier signal from the transceiver was not present
during transmission.
9
Late Collision. When set, indicates that the packet transmission was aborted after the collision
window of 64 bytes.
8
Excessive Collisions. When set, this bit indicates that the transmission was aborted after 16 collisions
while attempting to transmit the current packet.
7
Reserved. This bit is reserved. Always write zeros to this field to provide future compatibility.
6:3
Collision Count. This counter indicates the number of collisions that occurred before the packet was
transmitted. It is not valid when excessive collisions (bit 8) is also set.
2
Excessive Deferral. If the deferred bit is set in the control register, the setting of the excessive deferral
bit indicates that the transmission has ended because of a deferral of over 24288 bit times during
transmission.
1
Reserved. This bit is reserved. Always write zero to this bit to provide future compatibility.
0
Deferred. When set, this bit indicates that the current packet transmission was deferred.


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