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LAN9117 데이터시트(HTML) 48 Page - Microchip Technology

부품명 LAN9117
상세내용  High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
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제조사  MICROCHIP [Microchip Technology]
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LAN9117 데이터시트(HTML) 48 Page - Microchip Technology

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LAN9117
DS00002267A-page 48
 2005-2016 Microchip Technology Inc.
3.14.1.1
Receive Data FIFO Fast Forward
The RX data path implements an automatic data discard function. Using the RX data FIFO Fast Forward bit (RX_FFWD)
in the RX_DP_CTRL register, the host can instruct the LAN9117 to skip the packet at the head of the RX data FIFO.
The RX data FIFO pointers are automatically incremented to the beginning of the next RX packet.
When performing a fast-forward, there must be at least 4 DWORDs of data in the RX data FIFO for the packet being
discarded. For less than 4 DWORDs do not use RX_FFWD. In this case data must be read from the RX data FIFO and
discarded using standard PIO read operations.
After initiating a fast-forward operation, do not perform any reads of the RX data FIFO until the RX_FFWD bit is cleared.
Other resources can be accessed during this time (i.e., any registers and/or the other three FIFOs). Also note that the
RX_FFWD will only fast-forward the RX data FIFO, not the RX status FIFO.
The receiver does not have to be stopped to perform a fast-forward operation.
3.14.1.2
Force Receiver Discard (Receiver Dump)
In addition to the Receive data Fast Forward feature, LAN9117 also implements a receiver "dump" feature. This feature
allows the host processor to flush the entire contents of the RX data and RX status FIFOs. When activated, the read
and write pointers for the RX data and status FIFOs will be returned to their reset state. To perform a receiver dump, the
LAN9117 receiver must be halted. Once the receiver stop completion is confirmed, the RX_DUMP bit can be set in the
RX_CFG register. The RX_DUMP bit is cleared when the dump is complete. For more information on stopping the
receiver, please refer to Section 3.14.4, "Stopping and Starting the Receiver," on page 49. For more information on the
RX_DUMP bit, please refer to Section 5.3.7, "RX_CFG—Receive Configuration Register," on page 65.
3.14.2
RX PACKET FORMAT
The RX status words can be read from the RX status FIFO port, while the RX data packets can be read from the RX
data FIFO. RX data packets are formatted in a specific manner before the host can read them. It is assumed that the
host has previously read the associated status word from the RX status FIFO, to ascertain the data size and any error
conditions.
FIGURE 3-19:
RX PACKET FORMAT
ofs + First Data DWORD
.
.
.
.
Last Data DWORD
0
31
Host Read
Order
1st
2nd
Last
Optional Pad DWORD0
.
.
Optional Pad DWORDn
Optional offset DWORD0
.
.
Optional offset DWORDn


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