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LAN9117 데이터시트(HTML) 61 Page - Microchip Technology

부품명 LAN9117
상세내용  High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
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제조사  MICROCHIP [Microchip Technology]
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LAN9117 데이터시트(HTML) 61 Page - Microchip Technology

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 2005-2016 Microchip Technology Inc.
DS00002267A-page 61
LAN9117
5.3.1
ID_REV—CHIP ID AND REVISION
This register contains the ID and Revision fields for this design.
5.3.2
IRQ_CFG—INTERRUPT CONFIGURATION REGISTER
This register configures and indicates the state of the IRQ signal.
Offset:
50h
Size:
32 bits
Bits
Description
Type
Default
31-16
Chip ID. This read-only field identifies this design
RO
0117h
15-0
Chip Revision. This is the current revision of the chip.
RO
0001h
Offset:
54h
Size:
32 bits
Bits
Description
Type
Default
31:24
Interrupt Deassertion Interval (INT_DEAS). This field determines the
Interrupt Deassertion Interval for the Interrupt Request in multiples of 10
microseconds.
Writing zeros to this field disables the INT_DEAS Interval and resets the
interval counter. Any pending interrupts are then issued. If a new, non-
zero value is written to the INT_DEAS field, any subsequent interrupts will
obey the new setting.
Note:
The Interrupt Deassertion interval does not apply to the PME
interrupt.
R/W
0
23-15
Reserved
RO
-
14
Interrupt Deassertion Interval Clear (INT_DEAS_CLR). Writing a one to
this register clears the de-assertion counter in the IRQ Controller, thus
causing a new de-assertion interval to begin (regardless of whether or not
the IRQ Controller is currently in an active de-assertion interval).
SC
0
13
Interrupt Deassertion Status (INT_DEAS_STS). When set, this bit
indicates that the INT_DEAS is currently in a deassertion interval, and any
interrupts (as indicated by the IRQ_INT and INT_EN bits) will not be
delivered to the IRQ pin. When cleared, the INT_DEAS is currently not in
a deassertion interval, and enabled interrupts will be delivered to the IRQ
pin.
SC
0
12
Master Interrupt (IRQ_INT). This read-only bit indicates the state of the
internal IRQ line. When set high, one of the enabled interrupts is currently
active. This bit will respond to the associated interrupts regardless of the
IRQ_EN field. This bit is not affected by the setting of the INT_DEAS field.
RO
0
11-9
Reserved
RO
-
8
IRQ Enable (IRQ_EN) – This bit controls the final interrupt output to the
IRQ pin. When cleared, the IRQ output is disabled and will be
permanently deasserted. This bit only controls the external IRQ signal,
and has no effect on any of the internal interrupt status bits.
R/W
0
7-5
Reserved
RO
-
4
IRQ Polarity (IRQ_POL) – When cleared, enables the IRQ line to function
as an active low output. When set, the IRQ output is active high. When
IRQ is configured as an open-drain output this field is ignored, and the
interrupt output is always active low.
R/W NASR
0


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