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LAN9117 데이터시트(HTML) 62 Page - Microchip Technology

부품명 LAN9117
상세내용  High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
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제조사  MICROCHIP [Microchip Technology]
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LAN9117 데이터시트(HTML) 62 Page - Microchip Technology

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LAN9117
DS00002267A-page 62
 2005-2016 Microchip Technology Inc.
5.3.3
INT_STS—INTERRUPT STATUS REGISTER
This register contains the current status of the generated interrupts. Writing a 1 to the corresponding bits acknowledges
and clears the interrupt.
3-1
Reserved
RO
-
0
IRQ Buffer Type (IRQ_TYPE) – When cleared, enables IRQ to function
as an open-drain buffer for use in a Wired-Or Interrupt configuration.
When set, the IRQ output is a Push-Pull driver. When configured as an
open-drain output the IRQ_POL field is ignored, and the interrupt output
is always active low.
R/W NASR
0
Offset:
58h
Size:
32 bits
Bits
Description
Type
Default
31
Software Interrupt (SW_INT). This interrupt is generated when the
SW_INT_EN bit is set high. Writing a one clears this interrupt.
R/WC
0
30-26
Reserved
RO
-
25
TX Stopped (TXSTOP_INT). This interrupt is issued when STOP_TX bit in
TX_CFG is set, and the transmitter is halted.
R/WC
0
24
RX Stopped (RXSTOP_INT). This interrupt is issued when the receiver is
halted.
R/WC
0
23
RX Dropped Frame Counter Halfway (RXDFH_INT). This interrupt is
issued when the RX Dropped Frames Counter counts past its halfway point
(7FFFFFFFh to 80000000h).
R/WC
0
22
Reserved
RO
0
21
TX IOC Interrupt (TX_IOC). When a buffer with the IOC flag set has
finished being loaded into the TX FIFO, this interrupt is generated.
R/WC
0
20
RX DMA Interrupt (RXD_INT). This interrupt is issued when the amount of
data programmed in the RX DMA Count (RX_DMA_CNT) field of the
RX_CFG register has been transferred out of the RX FIFO.
R/WC
0
19
GP Timer (GPT_INT). This interrupt is issued when the General Purpose
timer wraps past zero to FFFFh.
R/WC
0
18
PHY (PHY_INT). Indicates a PHY Interrupt event.
RO
0
17
Power Management Event Interrupt (PME_INT). This interrupt is issued
when a Power Management Event is detected as configured in the
PMT_CTRL register. This interrupt functions independent of the PME
signal, and will still function if the PME signal is disabled. Writing a '1' clears
this bit regardless of the state of the PME hardware signal.
Notes:
• Detection of a Power Management Event, and assertion of the PME
signal will not wakeup the LAN9117. The LAN9117 will only wake up
when it detects a host write cycle of any data to the BYTE_TEST regis-
ter.
• The Interrupt Deassertion interval does not apply to the PME interrupt.
R/WC
0
16
TX Status FIFO Overflow (TXSO). Generated when the TX Status
FIFO overflows.
R/WC
0
15
Receive Watchdog Time-out (RWT). Interrupt is generated when a
packet larger than 2048 bytes has been received.
R/WC
0
14
Receiver Error (RXE). Indicates that the receiver has encountered an
error. Please refer to Section 3.14.5, "Receiver Errors," on page 50 for a
description of the conditions that will cause an RXE.
R/WC
0
Bits
Description
Type
Default


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