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LAN9117 데이터시트(HTML) 63 Page - Microchip Technology

부품명 LAN9117
상세내용  High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
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제조사  MICROCHIP [Microchip Technology]
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LAN9117 데이터시트(HTML) 63 Page - Microchip Technology

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 2005-2016 Microchip Technology Inc.
DS00002267A-page 63
LAN9117
5.3.4
INT_EN—INTERRUPT ENABLE REGISTER
This register contains the interrupt masks for IRQ. Writing 1 to any of the bits enables the corresponding interrupt as a
source for IRQ. Bits in the INT_STS register will still reflect the status of the interrupt source regardless of whether the
source is enabled as an interrupt in this register.
13
Transmitter Error (TXE). When generated, indicates that the transmitter
has encountered an error. Please refer to Section 3.13.7, "Transmitter
Errors," on page 46, for a description of the conditions that will cause a
TXE.
R/WC
0
12-11
Reserved
RO
-
10
TX Data FIFO Overrun Interrupt (TDFO). Generated when the TX data
FIFO is full, and another write is attempted.
R/WC
0
9
TX Data FIFO Available Interrupt (TDFA). Generated when the TX data
FIFO available space is greater than the programmed level.
R/WC
0
8
TX Status FIFO Full Interrupt (TSFF). Generated when the TX Status
FIFO is full.
R/WC
0
7
TX Status FIFO Level Interrupt (TSFL). Generated when the TX Status
FIFO reaches the programmed level.
R/WC
0
6
RX Dropped Frame Interrupt (RXDF_INT). This interrupt is issued
whenever a receive frame is dropped.
R/WC
0
5
Reserved
RO
-
4
RX Status FIFO Full Interrupt (RSFF). Generated when the RX Status
FIFO is full.
R/WC
0
3
RX Status FIFO Level Interrupt (RSFL). Generated when the RX Status
FIFO reaches the programmed level.
R/WC
0
2-0
GPIO [2:0] (GPIOx_INT). Interrupts are generated from the GPIO’s. These
interrupts are configured through the GPIO_CFG register.
R/WC
000
Offset:
5Ch
Size:
32 bits
Bits
Description
Type
Default
31
Software Interrupt (SW_INT_EN)
R/W
0
30:26
Reserved
RO
-
25
TX Stopped Interrupt Enable (TXSTOP_INT_EN)
R/W
0
24
RX Stopped Interrupt Enable (RXSTOP_INT_EN)
R/W
0
23
RX Dropped Frame Counter Halfway Interrupt Enable
(RXDFH_INT_EN).
R/W
0
22
Reserved
RO
0
21
TX IOC Interrupt Enable (TIOC_INT_EN)
R/W
0
20
RX DMA Interrupt (RXD_INT).
R/W
0
19
GP Timer (GPT_INT_EN)
R/W
0
18
PHY (PHY_INT_EN)
R/W
0
17
Power Management Event Interrupt Enable (PME_INT_EN)
R/W
0
16
TX Status FIFO Overflow (TXSO_EN)
R/W
0
15
Receive Watchdog Time-out Interrupt (RWT_INT_EN)
R/W
0
14
Receiver Error Interrupt (RXE_INT_EN)
R/W
0
13
Transmitter Error Interrupt (TXE_INT_EN)
R/W
0
12-11
Reserved
RO
-
10
TX Data FIFO Overrun Interrupt (TDFO_INT_EN)
R/W
0
Bits
Description
Type
Default


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