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LAN9117 데이터시트(HTML) 64 Page - Microchip Technology

부품명 LAN9117
상세내용  High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
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제조사  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
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LAN9117 데이터시트(HTML) 64 Page - Microchip Technology

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LAN9117
DS00002267A-page 64
 2005-2016 Microchip Technology Inc.
5.3.5
BYTE_TEST—BYTE ORDER TEST REGISTER
This register can be used to determine the byte ordering of the current configuration
5.3.6
FIFO_INT—FIFO LEVEL INTERRUPTS
This register configures the limits where the FIFO Controllers will generate system interrupts.
9
TX Data FIFO Available Interrupt (TDFA_INT_EN)
R/W
0
8
TX Status FIFO Full Interrupt (TSFF_INT_EN)
R/W
0
7
TX Status FIFO Level Interrupt (TSFL_INT_EN)
R/W
0
6
RX Dropped Frame Interrupt Enable (RXDF_INT_EN)
R/W
0
5
Reserved
RO
-
4
RX Status FIFO Full Interrupt (RSFF_INT_EN)
R/W
0
3
RX Status FIFO Level Interrupt (RSFL_INT_EN)
R/W
0
2-0
GPIO [2:0] (GPIOx_INT_EN).
R/W
000
Offset:
64h
Size:
32 bits
Bits
Description
Type
Default
31:0
Byte Test
RO
87654321h
Offset:
68h
Size:
32 bits
Bits
Description
Type
Default
31-24
TX Data Available Level. The value in this field sets the level, in number of
64 Byte blocks, at which the TX FIFO Available interrupt (TFDA) will be
generated. When the TX data FIFO free space is greater than this value a
TX FIFO Available interrupt (TDFA) will be generated.
R/W
48h
23-16
TX Status Level. The value in this field sets the level, in number of
DWORDs, at which the TX Status FIFO Level interrupt (TSFL) will be
generated. When the TX Status FIFO used space is greater than this value
an TX Status FIFO Level interrupt (TSFL) will be generated.
R/W
00h
15-8
Reserved
RO
-
7-0
RX Status Level. The value in this field sets the level, in number of
DWORDs, at which the RX Status FIFO Level interrupt (RSFL) will be
generated. When the RX Status FIFO used space is greater than this value
an RX Status FIFO Level interrupt (RSFL) will be generated.
R/W
00h
Bits
Description
Type
Default


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