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LAN9117 데이터시트(HTML) 66 Page - Microchip Technology

부품명 LAN9117
상세내용  High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
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LAN9117 데이터시트(HTML) 66 Page - Microchip Technology

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LAN9117
DS00002267A-page 66
 2005-2016 Microchip Technology Inc.
5.3.8
TX_CFG—TRANSMIT CONFIGURATION REGISTER
This register controls the transmit functions on the LAN9117 Ethernet Controller.
5.3.9
HW_CFG—HARDWARE CONFIGURATION REGISTER
This register controls the hardware configuration of the LAN9117 Ethernet Controller.
Offset:
70h
Size:
32 bits
Bits
Description
Type
Default
31-16
Reserved.
RO
-
15
Force TX Status Discard (TXS_DUMP). This self-clearing bit clears the TX
status FIFO of all pending status DWORD’s. When a ‘1’ is written, the TX
status pointers are cleared to zero.
SC
0
14
Force TX Data Discard (TXD_DUMP). This self-clearing bit clears the TX
data FIFO of all pending data. When a ‘1’ is written, the TX data pointers are
cleared to zero.
SC
0
13-3
Reserved
RO
-
2
TX Status Allow Overrun (TXSAO). When this bit is cleared, data
transmission is suspended if the TX Status FIFO becomes full. Setting this
bit high allows the transmitter to continue operation with a full TX Status
FIFO.
Note:
This bit does not affect the operation of the TX Status FIFO Full
interrupt.
R/W
0
1
Transmitter Enable (TX_ON). When this bit is set (1), the transmitter is
enabled. Any data in the TX FIFO will be sent. This bit is cleared
automatically when STOP_TX is set and the transmitter is halted.
R/W
0
0
Stop Transmitter (STOP_TX). When this bit is set (1), the transmitter will
finish the current frame, and will then stop transmitting. When the transmitter
has stopped this bit will clear. All writes to this bit are ignored while this bit
is high.
SC
0
Offset:
74h
Size:
32 bits
Note:
The transmitter and receiver must be stopped before writing to this register. Refer to Section 3.13.8, "Stop-
ping and Starting the Transmitter," on page 46 and Section 3.14.4, "Stopping and Starting the Receiver,"
on page 49 for details on stopping the transmitter and receiver.
Bits
Description
Type
Default
31-21
Reserved
RO
-
20
Must Be One (MBO). This bit must be set to “1” for normal device operation.
R/W
0
16-19
TX FIFO Size (TX_FIF_SZ). Sets the size of the TX FIFOs in 1KB values to
a maximum of 14KB. The TX Status FIFO consumes 512 bytes of the space
allocated by TX_FIF_SIZ, and the TX data FIFO consumes the remaining
space specified by TX_FIF_SZ. The minimum size of the TX FIFOs is 2KB
(TX data and status combined). The TX data FIFO is used for both TX data
and TX commands.
The RX Status and data FIFOs consume the remaining space, which is equal
to 16KB – TX_FIF_SIZ. See Section 5.3.9.1, "Allowable settings for
Configurable FIFO Memory Allocation," on page 68 for more information.
R/W
5h


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