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LAN9117 데이터시트(PDF) 67 Page - Microchip Technology

부품명 LAN9117
부품 상세설명  High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
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제조업체  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9117 데이터시트(HTML) 67 Page - Microchip Technology

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 2005-2016 Microchip Technology Inc.
DS00002267A-page 67
LAN9117
15-7
Reserved
RO
-
6-5
PHY Clock Select (PHY_CLK_SEL). This field is used to switch between
the internal and external MII clocks (RX_CLK and TX_CLK). This field is
encoded as follows:
[6]
[5]
MII Clock Source
---------------------------------------------------
0
0
Internal PHY
0
1
External MII Port
1
0
Clocks Disabled
1
1
Internal PHY
Note:
• This field does not control multiplexing of the SMI port or other MII sig-
nals.
• There are restrictions on the use of this field. Please refer to Section
3.12, "MII Interface - External MII Switching," on page 34 for details.
R/W
00b
4
Serial Management Interface Select (SMI_SEL). This bit is used to switch
the SMI port (MDIO and MDC) between the internal PHY and the external
MII port. When this bit is cleared to ‘0’, the internal PHY is selected, and all
SMI transactions will be to the internal PHY. When this bit is set to ‘1’, the
external MII port is selected, and all SMI transactions will be to the external
PHY. This bit functions independent of EXT_PHY_EN. When this bit is set,
the internal MDIO and MDC signals are driven low. When this bit is cleared,
the external MIDIO signal is tri-stated, and the MDC signal is driven low.
Note:
This bit does not control the multiplexing of other MII signals.
R/W
0
3
External PHY Detect (EXT_PHY_DET). This bit reflects the latched value
of the EXT_PHY_DET strap. The EXT_PHY_DET strap is used to indicate
the presence of an external PHY. This strap is latched from the value of the
external MDIO signal upon power-up or hard reset. If MDIO is pulled high a
‘1’ will be seen in this bit. If MDIO is pulled low a ‘0’ will be seen in this bit.
The RXT_PHY_DET strap has no other effect on the internal logic. Its only
function is to give the system designer a mechanism to indicate the presence
of an external PHY to a software application.
RO
Dependant on
EXT_PHY_D
ET strap pin
2
External PHY Enable (EXT_PHY_EN). When set to a ‘1’, this bit enables
the external MII port. When cleared, the internal PHY is enabled and the
external MII port is disabled.
Note:
• This signal does not control multiplexing of the SMI port or the TX_CLK
or RX_CLK signals.
• There are restrictions on the use of this bit. Please refer to Section 3.12,
"MII Interface - External MII Switching," on page 34 for details.
RW
0
1
Soft Reset Timeout (SRST_TO). If a software reset is attempted when the
internal PHY is not in the operational state (RX_CLK and TX_CLK running), the reset
will not complete and the soft reset operation will timeout and this bit will be set to a
‘1’. The host processor must correct the problem and issue another soft reset.
RO
0
Bits
Description
Type
Default


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