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LAN9117 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 68 Page - Microchip Technology

๋ถ€ํ’ˆ๋ช… LAN9117
์ƒ์„ธ๋‚ด์šฉ  High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
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LAN9117 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 68 Page - Microchip Technology

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LAN9117
DS00002267A-page 68
๏ƒฃ 2005-2016 Microchip Technology Inc.
5.3.9.1
Allowable settings for Configurable FIFO Memory Allocation
TX and RX FIFO space is configurable through the CSR - HW_CFG register defined above. The user must select the
FIFO allocation by setting the TX FIFO Size (TX_FIF_SZ) field in the hardware configuration (HW_CFG) register. The
TX_FIF_SZ field selects the total allocation for the TX data path, including the TX Status FIFO size. The TX Status FIFO
size is fixed at 512 Bytes (128 TX Status DWORDs). The TX Status FIFO length is subtracted from the total TX FIFO
size with the remainder being the TX data FIFO Size. Note that TX data FIFO space includes both commands and pay-
load data.
RX FIFO Size is the remainder of the unallocated FIFO space (16384 bytes โ€“ TX FIFO Size). The RX Status FIFO size
is always equal to 1/16 of the RX FIFO Size. The RX Status FIFO length is subtracted from the total RX FIFO size with
the remainder being the RX data FIFO Size.
For example, if TX_FIF_SZ = 6 then:
Total TX FIFO Size = 6144 Bytes (6KB)
TX Status FIFO Size = 512 Bytes (Fixed)
TX Data FIFO Size = 6144 โ€“ 512 = 5632 Bytes
RX FIFO Size = 16384 โ€“ 6144 = 10240 Bytes (10KB)
RX Status FIFO Size = 10240 / 16 = 640 Bytes (160 RX Status DWORDs)
RX Data FIFO Size = 10240 โ€“ 640 = 9600 Bytes
Table 5-3 shows every valid setting for the TX_FIF_SZ field. Note that settings not shown in this table are reserved and
should not be used.
0
Soft Reset (SRST). Writing 1 generates a software initiated reset. This reset
generates a full reset of the MAC CSRโ€™s. The SCSRโ€™s (system command
and status registers) are reset except for any NASR bits. Soft reset also
clears any TX or RX errors (TXE/RXE). This bit is self-clearing.
Note:
โ€ข Do not attempt a soft reset unless the internal PHY is fully awake and
operational. After a PHY reset, or when returning from a reduced power
state, the PHY must given adequate time to return to the operational
state before a soft reset can be issued. The internal RX_CLK and TX_-
CLK signals must be running for a proper software reset. Please refer to
Section 6.8, "Reset Timing," on page 103 for details on PHY reset timing.
โ€ข The LAN9117 must always be read at least once after power-up, reset,
or upon return from a power-saving state or write operations will not func-
tion.
SC
0
Note:
The RX data FIFO is considered full 4 DWORDs before the length that is specified in the HW_CFG register.
TABLE 5-3:
VALID TX/RX FIFO ALLOCATIONS
TX_FIF_SZ
TX Data FIFO Size
(Bytes)
TX Status FIFO Size
(Bytes)
RX Data FIFO Size
(Bytes)
RX Status FIFO Size
(Bytes)
2
1536
512
13440
896
3
2560
512
12480
832
4
3584
512
11520
768
5
4608
512
10560
704
6
5632
512
9600
640
7
6656
512
8640
576
8
7680
512
7680
512
9
8704
512
6720
448
10
9728
512
5760
384
Bits
Description
Type
Default


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