전자부품 데이터시트 검색엔진
  Korean  ▼

Delete All
ON OFF
ALLDATASHEET.CO.KR

X  

Preview PDF Download HTML

LAN9117 데이터시트(HTML) 69 Page - Microchip Technology

부품명 LAN9117
상세내용  High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Download  114 Pages
Scroll/Zoom Zoom In 100% Zoom Out
제조사  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
Logo 

LAN9117 데이터시트(HTML) 69 Page - Microchip Technology

Zoom Inzoom in Zoom Outzoom out
/ 114 page
 69 / 114 page
background image
 2005-2016 Microchip Technology Inc.
DS00002267A-page 69
LAN9117
In addition to the host-accessible FIFOs, the MAC Interface Layer (MIL) contains an additional 2K bytes of TX, and 128
bytes of RX FIFO buffering. These sizes are fixed, and cannot be adjusted by the host.
As space in the TX MIL (Mac Interface Layer) FIFO frees, data is moved into it from the TX data FIFO. Depending on
the size of the frames to be transmitted, the MIL can hold up to two Ethernet frames. This is in addition to any TX data
that may be queued in the TX data FIFO.
Conversely, as data is received by the LAN9117, it is moved from the MAC to the RX MIL FIFO, and then into the RX
data FIFO. When the RX data FIFO fills up, data will continue to collect in the RX MIL FIFO. If the RX MIL FIFO fills up
and overruns, subsequent RX frames will be lost until room is made in the RX data FIFO. For each frame of data that
is lost, the RX Dropped Frames Counter (RX_DROP) is incremented.
RX and TX MIL FIFO levels are not visible to the host processor. RX and TX MIL FIFOs operate independent of the TX
adatand RX data and status FIFOs. FIFO levels set for the RX and TX data and Status FIFOs do not take into consid-
eration the MIL FIFOs.
5.3.10
RX_DP_CTRL—RECEIVE DATAPATH CONTROL REGISTER
This register is used to discard unwanted receive frames.
11
10752
512
4800
320
12
11776
512
3840
256
13
12800
512
2880
192
14
13824
512
1920
128
Offset:
78h
Size:
32 bits
Bits
Description
Type
Default
31
RX Data FIFO Fast Forward (RX_FFWD): Writing a ‘1’ to this bit causes
the RX data FIFO to fast-forward to the start of the next frame. This bit will
remain high until the RX data FIFO fast-forward operation has completed.
No reads should be issued to the RX data FIFO while this bit is high.
Note:
Please refer to section “Receive Data FIFO Fast Forward” on
page 48 for detailed information regarding the use of RX_FFWD.
R/W
0h
30-0
Reserved
RO
-
TABLE 5-3:
VALID TX/RX FIFO ALLOCATIONS (CONTINUED)
TX_FIF_SZ
TX Data FIFO Size
(Bytes)
TX Status FIFO Size
(Bytes)
RX Data FIFO Size
(Bytes)
RX Status FIFO Size
(Bytes)


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62  63  64  65  66  67  68  69  70  71  72  73  74  75  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90  91  92  93  94  95  96  97  98  99  100   ...More


데이터시트 Download




링크 URL



Privacy Policy
ALLDATASHEET.CO.KR
ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ]  

Alldatasheet는?   |   광고문의    |   운영자에게 연락하기   |   개인정보취급방침   |   즐겨찾기   |   링크교환   |   제조사별 검색
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn