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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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LAN9117 데이터시트(HTML) 70 Page - Microchip Technology |
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LAN9117 데이터시트(HTML) 70 Page - Microchip Technology |
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LAN9117 DS00002267A-page 70 2005-2016 Microchip Technology Inc. 5.3.11 RX_FIFO_INF—RECEIVE FIFO INFORMATION REGISTER This register contains the used space in the receive FIFOs of the LAN9117 Ethernet Controller. 5.3.12 TX_FIFO_INF—TRANSMIT FIFO INFORMATION REGISTER This register contains the free space in the transmit data FIFO and the used space in the transmit status FIFO in the LAN9117. 5.3.13 PMT_CTRL— POWER MANAGEMENT CONTROL REGISTER This register controls the Power Management features. This register can be read while the LAN9117 is in a power saving mode. Offset: 7Ch Size: 32 bits Bits Description Type Default 31-24 Reserved RO - 23-16 RX Status FIFO Used Space (RXSUSED). Indicates the amount of space in DWORDs, used in the RX Status FIFO. RO 00h 15-0 RX Data FIFO Used Space (RXDUSED).). Reads the amount of space in bytes, used in the RX data FIFO. For each receive frame, this field is incremented by the length of the receive data rounded up to the nearest DWORD (if the payload does not end on a DWORD boundary). RO 0000h Offset: 80h Size: 32 bits Bits Description Type Default 31-24 Reserved RO - 23-16 TX Status FIFO Used Space (TXSUSED). Indicates the amount of space in DWORDS used in the TX Status FIFO. RO 00h 15-0 TX Data FIFO Free Space (TDFREE). Reads the amount of space in bytes, available in the TX data FIFO. The application should never write more data than is available, as indicated by this value. RO 1200h Offset: 84h Size: 32 bits Note: The LAN9117 must always be read at least once after power-up, reset, or upon return from a power-saving state or write operations will not function. |
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