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LAN9117 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 73 Page - Microchip Technology

๋ถ€ํ’ˆ๋ช… LAN9117
์ƒ์„ธ๋‚ด์šฉ  High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
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LAN9117 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 73 Page - Microchip Technology

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DS00002267A-page 73
LAN9117
5.3.15
GPT_CFG-GENERAL PURPOSE TIMER CONFIGURATION REGISTER
This register configures the General Purpose timer. The GP Timer can be configured to generate host interrupts at inter-
vals defined in this register.
10:8
GPIO Direction 0-2 (GPDIRn). When set, enables the corresponding GPIO as
output. When cleared the GPIO is enabled as an input.
GPIO0 โ€“ bit 8
GPIO1 โ€“ bit 9
GPIO2 โ€“ bit 10
R/W
0000
7:5
Reserved
RO
-
4:3
GPO Data 3-4 (GPODn). The value written is reflected on GPOn.
GPO3 โ€“ bit 3
GPO4 โ€“ bit 4
R/W
00
2:0
GPIO Data 0-2 (GPIODn). When enabled as an output, the value written is
reflected on GPIOn. When read, GPIOn reflects the current state of the
corresponding GPIO pin.
GPIO0 โ€“ bit 0
GPIO1 โ€“ bit 1
GPIO2 โ€“ bit 2
R/W
000
TABLE 5-4:
EEPROM ENABLE BIT DEFINITIONS
[22]
[21]
[20]
EEDIO Function
EECLK Function
0
0
0
EEDIO
EECLK
0
0
1
GPO3
GPO4
0
1
0
Reserved
0
1
1
GPO3
RX_DV
1
0
0
Reserved
1
0
1
TX_EN
GPO4
1
1
0
TX_EN
RX_DV
11
1
TX_CLK
RX_CLK
Offset:
8Ch
Size:
32 bits
Bits
Description
Type
Default
31-30
Reserved
RO
-
29
GP Timer Enable (TIMER_EN). When a one is written to this bit the GP
Timer is put into the run state. When cleared, the GP Timer is halted. On the
1 to 0 transition of this bit the GPT_LOAD field will be preset to FFFFh.
R/W
0
28-16
Reserved
RO
-
15-0
General Purpose Timer Pre-Load (GPT_LOAD). This value is pre-loaded
into the GP-Timer.
R/W
FFFFh
Bits
Description
Type
Default


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