전자부품 데이터시트 검색엔진
  Korean  ▼

Delete All
ON OFF
ALLDATASHEET.CO.KR

X  

Preview PDF Download HTML

LAN9117 데이터시트(HTML) 75 Page - Microchip Technology

부품명 LAN9117
상세내용  High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Download  114 Pages
Scroll/Zoom Zoom In 100% Zoom Out
제조사  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
Logo 

LAN9117 데이터시트(HTML) 75 Page - Microchip Technology

Zoom Inzoom in Zoom Outzoom out
/ 114 page
 75 / 114 page
background image
 2005-2016 Microchip Technology Inc.
DS00002267A-page 75
LAN9117
5.3.19
RX_DROP– RECEIVER DROPPED FRAMES COUNTER
This register indicates the number of receive frames that have been dropped.
5.3.20
MAC_CSR_CMD – MAC CSR SYNCHRONIZER COMMAND REGISTER
This register is used to control the read and write operations with the MAC CSR’s
5.3.21
MAC_CSR_DATA – MAC CSR SYNCHRONIZER DATA REGISTER
This register is used in conjunction with the MAC_CSR_CMD register to perform read and write operations with the MAC
CSR’s
5.3.22
AFC_CFG – AUTOMATIC FLOW CONTROL CONFIGURATION REGISTER
This register configures the mechanism that controls both the automatic, and software-initiated transmission of pause
frames and back pressure.
Offset:
A0h
Size:
32 bits
Bits
Description
Type
Default
31-0
RX Dropped Frame Counter (RX_DFC). This counter is incremented every
time a receive frame is dropped. RX_DFC is cleared on any read of this
register.
An interrupt can be issued when this counter passes through its halfway
point (7FFFFFFFh to 80000000h).
RC
00000000h
Offset:
A4h
Size:
32 bits
Bits
Description
Type
Default
31
CSR Busy. When a 1 is written into this bit, the read or write operation is
performed to the specified MAC CSR. This bit will remain set until the
operation is complete. In the case of a read this means that the host can
read valid data from the data register. The MAC_CSR_CMD and
MAC_CSR_DATA registers should not be modified until this bit is cleared.
SC
0
30
R/nW. When set, this bit indicates that the host is requesting a read
operation. When clear, the host is performing a write.
R/W
0
29-8
Reserved.
RO
-
7-0
CSR Address. The 8-bit value in this field selects which MAC CSR will be
accessed with the read or write operation.
R/W
00h
Offset:
A8h
Size:
32 bits
Bits
Description
Type
Default
31-0
MAC CSR Data. Value read from or written to the MAC CSR’s.
R/W
00000000h
Offset:
ACh
Size:
32 bits
Note:
The LAN9117 will not transmit pause frames or assert back pressure if the transmitter is disabled.


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62  63  64  65  66  67  68  69  70  71  72  73  74  75  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90  91  92  93  94  95  96  97  98  99  100   ...More


데이터시트 Download




링크 URL



Privacy Policy
ALLDATASHEET.CO.KR
ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ]  

Alldatasheet는?   |   광고문의    |   운영자에게 연락하기   |   개인정보취급방침   |   즐겨찾기   |   링크교환   |   제조사별 검색
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn