전자부품 데이터시트 검색엔진
  Korean  ▼

Delete All
ON OFF
ALLDATASHEET.CO.KR

X  

Preview PDF Download HTML

LAN9117 데이터시트(PDF) 76 Page - Microchip Technology

부품명 LAN9117
부품 상세설명  High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Download  114 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9117 데이터시트(HTML) 76 Page - Microchip Technology

Back Button LAN9117 Datasheet HTML 72Page - Microchip Technology LAN9117 Datasheet HTML 73Page - Microchip Technology LAN9117 Datasheet HTML 74Page - Microchip Technology LAN9117 Datasheet HTML 75Page - Microchip Technology LAN9117 Datasheet HTML 76Page - Microchip Technology LAN9117 Datasheet HTML 77Page - Microchip Technology LAN9117 Datasheet HTML 78Page - Microchip Technology LAN9117 Datasheet HTML 79Page - Microchip Technology LAN9117 Datasheet HTML 80Page - Microchip Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 76 / 114 page
background image
LAN9117
DS00002267A-page 76
 2005-2016 Microchip Technology Inc.
Bits
Description
Type
Default
31:24
Reserved
RO
-
23:16
Automatic Flow Control High Level (AFC_HI). Specifies, in multiples of 64
bytes, the level at which flow control will trigger. When this limit is reached
the chip will apply back pressure or will transmit a pause frame as
programmed in bits [3:0] of this register.
During full-duplex operation only a single pause frame is transmitted when
this level is reached. The pause time transmitted in this frame is
programmed in the FCPT field of the FLOW register in the MAC CSR space.
During half-duplex operation each incoming frame that matches the criteria
in bits [3:0] of this register will be jammed for the period set in the
BACK_DUR field.
R/W
00h
15:8
Automatic Flow Control Low Level (AFC_LO). Specifies, in multiples of 64
bytes, the level at which a pause frame is transmitted with a pause time
setting of zero. When the amount of data in the RX data FIFO falls below
this level the pause frame is transmitted. A pause time value of zero instructs
the other transmitting device to immediately resume transmission. The zero
time pause frame will only be transmitted if the RX data FIFO had reached
the AFC_HI level and a pause frame was sent. A zero pause time frame is
sent whenever automatic flow control in enabled in bits [3:0] of this register.
Note:
When automatic flow control is enabled the AFC_LO setting must
always be less than the AFC_HI setting.
R/W
00h
7:4
Backpressure Duration (BACK_DUR). When the LAN9117 automatically
asserts back pressure, it will be asserted for this period of time. This field
has no function and is not used in full-duplex mode. Please refer to Table 5-
5, describing Backpressure Duration bit mapping for more information.
R/W
0h
3
Flow Control on Multicast Frame (FCMULT). When this bit is set, the
LAN9117 will assert back pressure when the AFC level is reached and a
multicast frame is received. This field has no function in full-duplex mode.
R/W
0
2
Flow Control on Broadcast Frame (FCBRD). When this bit is set, the
LAN9117 will assert back pressure when the AFC level is reached and a
broadcast frame is received. This field has no function in full-duplex mode.
R/W
0
1
Flow Control on Address Decode (FCADD). When this bit is set, the
LAN9117 will assert back pressure when the AFC level is reached and a
frame addressed to the LAN9117 is received. This field has no function in
full-duplex mode.
R/W
0
0
Flow Control on Any Frame (FCANY). When this bit is set, the LAN9117
will assert back pressure, or transmit a pause frame when the AFC level is
reached and any frame is received. Setting this bit enables full-duplex flow
control when the LAN9117 is operating in full-duplex mode.
When this mode is enabled during half-duplex operation, the Flow Controller
does not decode the MAC address and will send a pause frame upon receipt
of a valid preamble (i.e., immediately at the beginning of the next frame after
the RX data FIFO level is reached).
When this mode is enabled during full-duplex operation, the Flow Controller
will immediately instruct the MAC to send a pause frame when the RX data
FIFO level is reached. The MAC will queue the pause frame transmission for
the next available window.
Setting this bit overrides bits [3:1] of this register.
R/W
0


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62  63  64  65  66  67  68  69  70  71  72  73  74  75  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90  91  92  93  94  95  96  97  98  99  100   ...More


데이터시트 다운로드

Go To PDF Page


링크 URL




개인정보취급방침
ALLDATASHEET.CO.KR
ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn