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LAN9117 데이터시트(HTML) 82 Page - Microchip Technology

부품명 LAN9117
상세내용  High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
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제조사  MICROCHIP [Microchip Technology]
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LAN9117 데이터시트(HTML) 82 Page - Microchip Technology

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LAN9117
DS00002267A-page 82
 2005-2016 Microchip Technology Inc.
5.4.2
ADDRH—MAC ADDRESS HIGH REGISTER
The MAC Address High register contains the upper 16-bits of the physical address of the MAC. The contents of this
register are optionally loaded from the EEPROM at power-on through the EEPROM Controller if a programmed
EEPROM is detected. The least significant byte of this register (bits [7:0]) is loaded from address 0x05 of the EEPROM.
The second byte (bits [15:8]) is loaded from address 0x06 of the EEPROM. Please refer to Section 4.6 for more infor-
mation on the EEPROM. Section 5.4.3 details the byte ordering of the ADDRL and ADDRH registers with respect to the
reception of the Ethernet physical address.
5.4.3
ADDRL—MAC ADDRESS LOW REGISTER
The MAC Address Low register contains the lower 32 bits of the physical address of the MAC. The contents of this reg-
ister are optionally loaded from the EEPROM at power-on through the EEPROM Controller if a programmed EEPROM
is detected. The least significant byte of this register (bits [7:0]) is loaded from address 0x01 of the EEPROM. The most
significant byte of this register is loaded from address 0x04 of the EEPROM. Please refer to Section 4.6 for more infor-
mation on the EEPROM.
5
Deferral Check (DFCHK). When set, enables the deferral check in the MAC. The MAC will abort the
transmission attempt if it has deferred for more than 24,288 bit times. Deferral starts when the
transmitter is ready to transmit, but is prevented from doing so because the CRS is active. Defer time
is not cumulative. If the transmitter defers for 10,000 bit times, then transmits, collides, backs off, and
then has to defer again after completion of back-off, the deferral timer resets to 0 and restarts. When
reset, the deferral check is disabled in the MAC and the MAC defers indefinitely.
4
Reserved
3
Transmitter enable (TXEN). When set, the MAC’s transmitter is enabled and it will transmit frames
from the buffer onto the cable.
When reset, the MAC’s transmitter is disabled and will not transmit any frames.
2
Receiver Enable (RXEN). When set (1), the MAC’s receiver is enabled and will receive frames from
the internal PHY.
When reset, the MAC’s receiver is disabled and will not receive any frames from the internal PHY.
1-0
Reserved
Offset:
2
Attribute:
R/W
Default Value:
0000FFFFh
Size:
32 bits
Bits
Description
31-16
Reserved
15-0
Physical Address [47:32]. This field contains the upper 16-bits (47:32) of the Physical Address of the
LAN9117 device. The content of this field is undefined until loaded from the EEPROM at power-on.
The host can update the contents of this field after the initialization process has completed.
Offset:
3
Attribute:
R/W
Default Value:
FFFFFFFFh
Size:
32 bits
Bits
Description
31-0
Physical Address [31:0]. This field contains the lower 32 bits (31:0) of the Physical Address of the
LAN9117 device. The content of this field is undefined until loaded from the EEPROM at power-on.
The host can update the contents of this field after the initialization process has completed.
Bits
Description


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