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์ ์๋ถํ ๋ฐ์ดํฐ์ํธ ๊ฒ์์์ง |
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LAN9117 ๋ฐ์ดํฐ์ํธ(HTML) 9 Page - Microchip Technology |
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LAN9117 ๋ฐ์ดํฐ์ํธ(HTML) 9 Page - Microchip Technology |
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๏ฃ 2005-2016 Microchip Technology Inc. DS00002267A-page 9 LAN9117 TABLE 2-1: HOST BUS INTERFACE SIGNALS Pin No. Name Symbol Buffer Type # Pins Description 43-46,49- 53,56-59,62- 64 Host Data D[15:0] I/O8 16 Bi-directional data port. 12-18 Host Address A[7:1] IS 7 7-bit Address Port. Used to select Internal CSRโs and TX and RX FIFOs. 92 Read Strobe nRD IS 1 Active low strobe to indicate a read cycle. 93 Write Strobe nWR IS 1 Active low strobe to indicate a write cycle. This signal, qualified with nCS, is also used to wakeup the LAN9117 when it is in a reduced power state. 94 Chip Select nCS IS 1 Active low signal used to qualify read and write operations. This signal qualified with nWR is also used to wakeup the LAN9117 when it is in a reduced power state. 72 Interrupt Request IRQ O8/OD8 1 Programmable Interrupt request. Programmable polarity, source and buffer types. 76 FIFO Select FIFO_SEL IS 1 When driven high all accesses to the LAN9117 are to the RX or TX Data FIFOs. In this mode, the A[7:3] upper address inputs are ignored. TABLE 2-2: DEFAULT ETHERNET SETTINGS Default Ethernet Settings SPEED_SEL Speed Duplex Auto Neg. 0 10MBPS HALF-DUPLEX DISABLED 1 100MBPS HALF-DUPLEX ENABLED TABLE 2-3: LAN INTERFACE SIGNALS Pin No. Name Symbol Buffer Type # Pins Description 79 TXP TPO+ AO 1 Twisted Pair Transmit Output, Positive 78 TXN TPO- AO 1 Twisted Pair Transmit Output, Negative 83 RXP TPI+ AI 1 Twisted Pair Receive Input, Positive 82 RXN TPI- AI 1 Twisted Pair Receive Input, Negative 87 PHY External Bias Resistor EXRES1 AI 1 Must be connected to ground through a 12.4K ohm 1% resistor. |
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