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LAN9117 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 92 Page - Microchip Technology

๋ถ€ํ’ˆ๋ช… LAN9117
์ƒ์„ธ๋‚ด์šฉ  High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
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์ œ์กฐ์‚ฌ  MICROCHIP [Microchip Technology]
ํ™ˆํŽ˜์ด์ง€  http://www.microchip.com
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LAN9117 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 92 Page - Microchip Technology

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LAN9117
DS00002267A-page 92
๏ƒฃ 2005-2016 Microchip Technology Inc.
5.5.8
MODE CONTROL/STATUS
5.5.9
SPECIAL MODES
1
Page Received.
1 = new page received
0 = new page not yet received
RO/LH
0
0
Link Partner Auto-Negotiation Able.
1 = link partner has auto-negotiation ability
0 = link partner does not have auto-negotiation ability
RO
0
Index (In Decimal):
17
Size:
16-bits
Bits
Description
Type
Default
15-14
Reserved. Write as 0; ignore on read.
RW
0
13
EDPWRDOWN. Enable the Energy Detect Power-Down mode:
0=Energy Detect Power-Down is disabled
1=Energy Detect Power-Down is enabled
RW
0
12-2
Reserved. Write as 0, ignore on read
RW
0
1
ENERGYON. Indicates whether energy is detected This bit goes to a โ€œ0โ€ if
no valid energy is detected within 256ms. Reset to โ€œ1โ€ by hardware reset,
unaffected by SW reset.
RO
1
0
Reserved. Write as โ€œ0โ€. Ignore on read.
RW
0
Index (In Decimal):
18
Size:
16-bits
Address
Description
Type
Default
15-8
Reserved
RW,
NASR
7:5
MODE: PHY Mode of operation. Refer to Table 5-9 for more details.
RW,
NASR
See
Table 5-9
4:0
PHYAD: PHY Address:
The PHY Address is used for the SMI address.
RW,
NASR
00001b
TABLE 5-9:
MODE CONTROL
Mode
Mode Definitions
Default Register Bit Values
Register 0
Register 4
[13,12,10,8]
[8,7,6,5]
000
10Base-T Half Duplex. Auto-negotiation disabled.
0000
N/A
001
10Base-T Full Duplex. Auto-negotiation disabled.
0001
N/A
010
100Base-TX Half Duplex. Auto-negotiation disabled.
CRS is active during Transmit & Receive.
1000
N/A
011
100Base-TX Full Duplex. Auto-negotiation disabled.
CRS is active during Receive.
1001
N/A
Bits
Description
Type
Default


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