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LAN9117 데이터시트(PDF) 96 Page - Microchip Technology

부품명 LAN9117
부품 상세설명  High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
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제조업체  MICROCHIP [Microchip Technology]
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LAN9117 데이터시트(HTML) 96 Page - Microchip Technology

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LAN9117
DS00002267A-page 96
 2005-2016 Microchip Technology Inc.
6.1.2
SPECIAL RESTRICTIONS ON BACK-TO-BACK READ CYCLES
There are also restrictions on specific back-to-back read operations. These restrictions concern reading specific regis-
ters after reading resources that have side effects. In many cases there is a delay between reading the LAN9117, and
the subsequent indication of the expected change in the control register values.
In order to prevent the host from reading stale data on back-to-back reads, minimum wait periods have been estab-
lished. These periods are specified in Table 6-2, "Read After Read Timing Rules". The host processor is required to wait
the specified period of time between read operations of specific combinations of resources. The wait period is depen-
dent upon the combination of registers being read.
Performing "dummy" reads of the BYTE_TEST register is a convenient way to ensure that the minimum wait time restric-
tion is met. Table 6-2 also shows the number of dummy reads that are required for back-to-back read operations. The
number of BYTE_TEST reads in this table is based on the minimum timing for Tcycle (45ns). For microprocessors with
slower busses the number of reads may be reduced as long as the total time is equal to, or greater than the time spec-
ified in the table. Dummy reads of the BYTE_TEST register are not required as long as the minimum time period is met.
TABLE 6-1:
READ AFTER WRITE TIMING RULES
Register Name
Minimum Wait Time for Read Following
Any Write Cycle
(in ns)
Number of BYTE_TEST Reads
(Assuming Tcycle of 45ns)
ID_REV
0
0
IRQ_CFG
135
3
INT_STS
90
2
INT_EN
45
1
BYTE_TEST
0
0
FIFO_INT
45
1
RX_CFG
45
1
TX_CFG
45
1
HW_CFG
45
1
RX_DP_CTRL
45
1
RX_FIFO_INF
0
0
TX_FIFO_INF
135
3
PMT_CTRL
315
7
GPIO_CFG
45
1
GPT_CFG
45
1
GPT_CNT
135
3
WORD_SWAP
45
1
FREE_RUN
180
4
RX_DROP
0
0
MAC_CSR_CMD
45
1
MAC_CSR_DATA
45
1
AFC_CFG
45
1
E2P_CMD
45
1
E2P_DATA
45
1


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