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LAN9117 데이터시트(HTML) 97 Page - Microchip Technology

부품명 LAN9117
상세내용  High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
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제조사  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
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LAN9117 데이터시트(HTML) 97 Page - Microchip Technology

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 2005-2016 Microchip Technology Inc.
DS00002267A-page 97
LAN9117
6.2
PIO Reads
PIO reads can be used to access CSRs or RX Data and RX/TX status FIFOs. In this mode, counters in the CSRs are
latched at the beginning of the read cycle. Read data is valid as indicated in the timing diagram. PIO reads can be per-
formed using Chip Select (nCS) or Read Enable (nRD). Either or both of these control signals must go high between
cycles for the period specified.
TABLE 6-2:
READ AFTER READ TIMING RULES
After Reading...
Wait for this Many ns…
or Perform this Many Reads of
BYTE_TEST…
(Assuming Tcycle of 45ns)
Before Reading...
RX Data FIFO
135
3
RX_FIFO_INF
RX Status FIFO
135
3
RX_FIFO_INF
TX Status FIFO
135
3
TX_FIFO_INF
RX_DROP
180
4
RX_DROP
Note:
Some registers have restrictions on the timing of back-to-back, write-read and read-read cycles.
FIGURE 6-1:
LAN9117 PIO READ CYCLE TIMING
Note:
The “Data Bus” width is 16 bits.
TABLE 6-3:
PIO READ TIMING
Symbol
Description
MIN
TYP
MAX
Units
tcycle
Read Cycle Time
45
ns
tcsl
nCS, nRD Assertion Time
32
ns
tcsh
nCS, nRD Deassertion Time
13
ns
tcsdv
nCS, nRD Valid to Data Valid
30
ns
tasu
Address Setup to nCS, nRD Valid
0
ns
tah
Address Hold Time
0
ns
tdon
Data Buffer Turn On Time
0
ns
tdoff
Data Buffer Turn Off Time
7
ns
tdoh
Data Output Hold Time
0
ns
Data Bus
nCS, nRD
A[7:1]


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