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LAN9117 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 98 Page - Microchip Technology

๋ถ€ํ’ˆ๋ช… LAN9117
์ƒ์„ธ๋‚ด์šฉ  High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
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LAN9117 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 98 Page - Microchip Technology

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LAN9117
DS00002267A-page 98
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6.3
PIO Burst Reads
In this mode, performance is improved by allowing up to 16, WORD read cycles back-to-back. PIO Burst Reads can be
performed using Chip Select (nCS) or Read Enable (nRD). Either or both of these control signals must go high between
bursts for the period specified.
Note:
A PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both nCS
and nRD are deasserted. They may be asserted and deasserted in any order.
FIGURE 6-2:
LAN9117 PIO BURST READ CYCLE TIMING
Note:
The โ€œData Busโ€ width is 16 bits.
TABLE 6-4:
PIO BURST READ TIMING
Symbol
Description
MIN
TYP
MAX
Units
tcsh
nCS, nRD Deassertion Time
13
ns
tcsdv
nCS, nRD Valid to Data Valid
30
ns
tacyc
Address Cycle Time
45
tasu
Address Setup to nCS, nRD valid
0
ns
tadv
Address Stable to Data Valid
40
tah
Address Hold Time
0
ns
tdon
Data Buffer Turn On Time
0
ns
tdoff
Data Buffer Turn Off Time
7
ns
tdoh
Data Output Hold Time
0
ns
Note:
A PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both
nCS and nRD are deasserted. They may be asserted and deasserted in any order.
Data Bus
nCS, nRD
A[7:5]
A[4:1]


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