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LAN9117 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 99 Page - Microchip Technology

๋ถ€ํ’ˆ๋ช… LAN9117
์ƒ์„ธ๋‚ด์šฉ  High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
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LAN9117 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 99 Page - Microchip Technology

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DS00002267A-page 99
LAN9117
6.4
RX Data FIFO Direct PIO Reads
In this mode the upper address inputs are not decoded, and any read of the LAN9117 will read the RX Data FIFO. This
mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the
FIFO_SEL signal to high-order address line. This mode is useful when the host processor must increment its address
when accessing the LAN9117. Timing is identical to a PIO read, and the FIFO_SEL signal has the same timing charac-
teristics as the address lines.
Note that address lines A[2:1] are still used, and address bits A[7:3] are ignored.
FIGURE 6-3:
RX DATA FIFO DIRECT PIO READ CYCLE TIMING
Note:
The โ€œData Busโ€ width is 16 bits.
TABLE 6-5:
RX DATA FIFO DIRECT PIO READ TIMING
Symbol
Description
MIN
TYP
MAX
Units
tcycle
Read Cycle Time
45
ns
tcsl
nCS, nRD Assertion Time
32
ns
tcsh
nCS, nRD Deassertion Time
13
ns
tcsdv
nCS, nRD Valid to Data Valid
30
ns
tasu
Address, FIFO_SEL Setup to nCS, nRD Valid
0
ns
tah
Address, FIFO_SEL Hold Time
0
ns
tdon
Data Buffer Turn On Time
0
ns
tdoff
Data Buffer Turn Off Time
7
ns
tdoh
Data Output Hold Time
0
ns
Note:
An RX Data FIFO Direct PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends
when either or both nCS and nRD are de-asserted. They may be asserted and de-asserted in any order.
Data Bus
nCS, nRD
FIFO_SEL
A[2:1]


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