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LAN9117 ๋ฐ์ดํฐ์ํธ(HTML) 100 Page - Microchip Technology |
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LAN9117 ๋ฐ์ดํฐ์ํธ(HTML) 100 Page - Microchip Technology |
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100 / 114 page 
LAN9117 DS00002267A-page 100 ๏ฃ 2005-2016 Microchip Technology Inc. 6.5 RX Data FIFO Direct PIO Burst Reads In this mode the upper address inputs are not decoded, and any burst read of the LAN9117 will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9117. Timing is identical to a PIO Burst Read, and the FIFO_SEL signal has the same timing characteristics as the address lines. In this mode, performance is improved by allowing an unlimited number of back-to-back DWORD or WORD read cycles. RX Data FIFO Direct PIO Burst Reads can be performed using Chip Select (nCS) or Read Enable (nRD). When either or both of these control signals go high, they must remain high for the period specified. Note that address lines A[2:1] are still used, and address bits A[7:3] are ignored. FIGURE 6-4: RX DATA FIFO DIRECT PIO BURST READ CYCLE TIMING Note: The โData Busโ width is 16 bits. FIGURE 6-5: RX DATA FIFO DIRECT PIO BURST READ CYCLE TIMING Symbol Description MIN TYP MAX Units tcsh nCS, nRD Deassertion Time 13 ns tcsdv nCS, nRD Valid to Data Valid 30 ns tacyc Address Cycle Time 45 tasu Address, FIFO_SEL Setup to nCS, nRD Valid 0 ns tadv Address Stable to Data Valid 40 tah Address, FIFO_SEL Hold Time 0 ns tdon Data Buffer Turn On Time 0 ns tdoff Data Buffer Turn Off Time 7 ns tdoh Data Output Hold Time 0 ns Note: An RX Data FIFO Direct PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and deasserted in any order. Data Bus nCS, nRD FIFO_SEL A[2:1] |
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