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์ ์๋ถํ ๋ฐ์ดํฐ์ํธ ๊ฒ์์์ง |
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์ ์๋ถํ ๋ฐ์ดํฐ์ํธ ๊ฒ์์์ง |
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LAN9117 ๋ฐ์ดํฐ์ํธ(HTML) 12 Page - Microchip Technology |
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LAN9117 ๋ฐ์ดํฐ์ํธ(HTML) 12 Page - Microchip Technology |
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12 / 114 page 
LAN9117 DS00002267A-page 12 ๏ฃ 2005-2016 Microchip Technology Inc. 100, 99, 98 General Purpose I/O data, nLED1 (Speed Indicator), nLED2 (Link & Activity Indicator), nLED3 (Full- Duplex Indicator). GPIO[2:0]/ LED[3:1] IS/O12/ OD12 3 General Purpose I/O data: These three general-purpose signals are fully programmable as either push-pull output, open-drain output or input by writing the GPIO_CFG configuration register in the CSRโs. They are also multiplexed as GP LED connections. GPIO signals are Schmitt-triggered inputs. When configured as LED outputs these signals are open-drain. nLED1 (Speed Indicator). This signal is driven low when the operating speed is 100Mbs, during auto-negotiation and when the cable is disconnected. This signal is driven high only during 10Mbs operation. nLED2 (Link & Activity Indicator). This signal is driven low (LED on) when the LAN9117 detects a valid link. This signal is pulsed high (LED off) for 80mS whenever transmit or receive activity is detected. This signal is then driven low again for a minimum of 80mS, after which time it will repeat the process if TX or RX activity is detected. Effectively, LED2 is activated solid for a link. When transmit or receive activity is sensed LED2 will flash as an activity indicator. nLED3 (Full-Duplex Indicator). This signal is driven low when the link is operating in full-duplex mode. 10 RBIAS RBIAS AI 1 PLL Bias: Connect to an external 12.0K ohm 1.0% resistor to ground. Used for the PLL Bias circuit. 9 Test Pin ATEST I 1 This pin must be connected to VDD for normal operation. 2 Internal Regulator Power VREG P 1 3.3V input for internal voltage regulator 20,28,3 5, 42,48,5 5,61,97 +3.3V I/O Power VDD_IO P 8 +3.3V I/O logic power supply pins 19,27,3 4,41,47, 54,60,9 6 I/O Ground GND_IO P 8 Ground for I/O pins 81,85,8 9 +3.3V Analog Power VDD_A P 3 +3.3V Analog power supply pins. See Note 2-1 77,80,8 6,88 Analog Ground VSS_A P 4 Ground for analog circuitry 3,65 Core Voltage Decoupling VDD_CORE P 2 1.8 V from internal core regulator. Both pins must be connected together externally and then tied to a 10uF 0.1- Ohm ESR capacitor, in parallel with a 0.01uF capacitor to Ground next to each pin. These pins must not be used to supply power to other external devices. See Note 2-1 TABLE 2-5: SYSTEM AND POWER SIGNALS (CONTINUED) Pin No. Name Symbol Buffer Type # Pins Description |
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