전자부품 데이터시트 검색엔진 |
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ADS8401 데이터시트(PDF) 5 Page - Burr-Brown (TI) |
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ADS8401 데이터시트(HTML) 5 Page - Burr-Brown (TI) |
5 / 10 page ADS8401 SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 www.ti.com 5 TIMING CHARACTERISTICS All specifications typical at –40 °C to 85°C, +VA = +VBD = 5 V (see Notes 1, 2, and 3) PARAMETER MIN TYP MAX UNIT tCONV Conversion time 600 610 ns tACQ Acquisition time 150 ns tpd1 CONVST low to conversion started (BUSY high) 35 ns tpd2 Propagation delay time, End of conversion to BUSY low 20 ns tw1 Pulse duration, CONVST low 20 ns tsu1 Setup time, CS low to CONVST low 0 ns tw2 Pulse duration, CONVST high 20 ns CONVST falling edge jitter 10 ps tw3 Pulse duration, BUSY signal low Min(tACQ) ns tw4 Pulse duration, BUSY signal high 630 ns th1 Hold time, First data bus data transition (RD low, or CS low for read cycle, or BYTE input changes) after CONVST low 40 ns td1 Delay time, CS low to RD low 0 ns tsu2 Setup time, RD high to CS high 0 ns tw5 Pulse duration, RD low time 50 ns ten Enable time, RD low (or CS low for read cycle) to data valid 20 ns td2 Delay time, data hold from RD high 0 ns td3 Delay time, BYTE rising edge or falling edge to data valid 2 20 ns tw6 RD high 20 ns th2 Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge 50 ns tpd4 Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling edge Max(td5) ns tsu3 Setup time, BYTE rising edge to RD falling edge 0 ns th3 Hold time, BYTE falling edge to RD falling edge 0 ns tdis Disable time, RD High (CS high for read cycle) to 3-stated data bus 20 ns td5 Delay time, BUSY low to MSB data valid 0 ns tsu4 Setup time, BYTE change before BUSY falling edge 2 20 ns (1) All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2. (2) See timing diagrams. (3) All timings are measured with 20 pF equivalent loads on all data bits and BUSY pins. |
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유사한 설명 - ADS8401 |
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