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LM3543MX-H 데이터시트(PDF) 10 Page - National Semiconductor (TI) |
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LM3543MX-H 데이터시트(HTML) 10 Page - National Semiconductor (TI) |
10 / 12 page Application Information (Continued) tantalum capacitor is recommended. The input supply should be further bypassed with a 0.01 µF - 0.1 µF ceramic capacitor, placed close to the device. The ceramic capacitor reduces ringing on the supply that can occur when a short is present at the output of a port. Extending the Fault Flag Delay While the 7 ms (typical) internal delay in reporting flag conditions is adequate for most applications, the delay can be extended by connecting external RC filters to the FLAG pins, as shown in Figure 5. Power Dissipation and Junction Temperature A few simple calculations will allow a designer to calculate the approximate operating temperature of the LM3543 for a given application. The large currents possible through the low resistance power MOSFET combined with the high thermal resistance of the SOIC package, in relation to power packages, make this estimate an important design step. Begin the estimate by determining R ON at the expected operating temperature using the graphs in the Typical Performance Characteristics section of this datasheet. Next, calculate the power dissipation through the switch with Equation (1). PD=R ON * IDS 2 (1) Note: Equation for power dissipation neglects portion that comes from LM3543 quiescent current because this value will almost always be insignificant. Using this figure, determine the junction temperature with Equation (2). T J =PD * θJA +TA. (2) Where: θ JA = SOIC Thermal Resistance: 130˚C/W and TA = Ambient Temperature (˚C). Compare the calculated temperature with the expected temperature used to estimate R ON. If they do not reasonably match, re-estimate R ON using a more appropriate operating temperature and repeat the calculations. Reiterate as necessary. PCB Layout Considerations In order to meet the USB requirements for voltage drop, droop and EMI, each component used in this circuit must be evaluated for its contribution to the circuit performance. These principles are illustrated in Figure 6. The following PCB layout rules and guidelines are recommended 1. Place the switch as close to the USB connector as possible. Keep all V bus traces as short as possible and use at least 50-mil, 1 ounce copper for all V bus traces. Solder plating the traces will reduce the trace resistance. 2. Avoid vias as much as possible. If vias are used, use multiple vias in parallel and/or make them as large as possible. 3. Place the output capacitor and ferrite beads as close to the USB connector as possible. 4. If ferrite beads are used, use wires with minimum resistance and large solder pads to minimize connection resistance. 10125828 FIGURE 5. Typical Circuit for Lengthening the Internal Flag Delay 10125827 FIGURE 6. Self-Powered Hub Connections and Per-Port Voltage Drop www.national.com 10 |
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