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AD7616 데이터시트(PDF) 10 Page - Analog Devices |
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AD7616 데이터시트(HTML) 10 Page - Analog Devices |
10 / 51 page Data Sheet AD7616 Rev. 0 | Page 9 of 50 Serial Mode Timing Specifications Table 4. Parameter Min Typ Max Unit Description fSCLK1 40/50 MHz SCLK frequency tSCLK 1/fSCLK Minimum SCLK period tSCLK_SETUP1 10.5 ns CS to SCLK falling edge setup time, VDRIVE above 3 V 13.5 ns CS to SCLK falling edge setup time, VDRIVE above 2.3 V tSCLK_HOLD 10 ns SCLK to CS rising edge hold time tSCLK_LOW 8 ns SCLK low pulse width tSCLK_HIGH 9 ns SCLK high pulse width tDOUT_SETUP1 9 ns Data out access time after SCLK rising edge, VDRIVE above 3 V 11 ns Data out access time after SCLK rising edge, VDRIVE above 2.3 V tDOUT_HOLD 4 ns Data out hold time after SCLK rising edge tDIN_SETUP 10 ns Data in setup time before SCLK falling edge tDIN_HOLD 8 ns Data in hold time after SCLK falling edge tDOUT_3STATE 10 ns CS rising edge to SDOx high impedance 1 Dependent on VDRIVE and load capacitance (see Table 14). Figure 6. Serial Timing Diagram CONVST BUSY CS 1 2 3 14 15 16 SCLK DB15 DB14 DB13 DB15 DB14 DB13 DB15 DB14 DB13 DB2 DB1 DB0 DB2 DB1 DB0 DB2 DB1 DB0 SDOA SDOB SDI t DOUT_SETUP t DOUT_HOLD t SCLK_SETUP t SCLK t SCLK_HIGH t SCLK_LOW t SCLK_HOLD t DIN_HOLD t DIN_SETUP t DOUT_3STATE |
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