6.8 GHz Wideband Synthesizer

with Integrated VCO

Data Sheet

ADF4356

Rev. 0

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FEATURES

RF output frequency range: 53.125 MHz to 6800 MHz

Integer channel: −227 dBc/Hz

Fractional channel: −225 dBc/Hz

Integrated RMS jitter (1 kHz to 20 MHz): 97 fs for 6 GHz output

Fractional-N synthesizer and integer-N synthesizer

Pin compatible to the ADF4355

High resolution, 52-bit modulus

Phase frequency detector (PFD) operation to 125 MHz

Reference input frequency operation to 600 MHz

Maintains frequency lock over −40°C to +85°C

Low phase noise, voltage controlled oscillator (VCO)

Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output

Analog and digital power supplies: 3.3 V

Charge pump and VCO power supplies: 5.0 V typical

Logic compatibility: 1.8 V

Programmable output power level

RF output mute function

Supported in the ADIsimPLL design tool

APPLICATIONS

Wireless infrastructure (LTE, W-CDMA, TD-SCDMA,

WiMAX, GSM, PCS, DCS)

Point to point/point to multipoint microwave links

Satellites/VSATs

Test equipment/instrumentation

Clock generation

GENERAL DESCRIPTION

The ADF4356 allows implementation of fractional-N or integer-N

phase-locked loop (PLL) frequency synthesizers when used with

an external loop filter and an external reference frequency. A series

of frequency dividers at another frequency output permits

operation from 53.125 MHz to 6800 MHz.

The ADF4356 has an integrated VCO with a fundamental

output frequency ranging from 3400 MHz to 6800 MHz. In

addition, the VCO frequency is connected to divide by 1, 2, 4, 8,

16, 32, or 64 circuits that allow the user to generate RF output

frequencies as low as 53.125 MHz. For applications that require

isolation, the RF output stage can be muted. The mute function

is both pin- and software-controllable.

Control of all on-chip registers is through a simple 3-wire interface.

The ADF4356 operates with analog and digital power supplies

ranging from 3.15 V to 3.45 V, with charge pump and VCO

supplies from 4.75 V to 5.25 V. The ADF4356 also contains

hardware and software power-down modes.

FUNCTIONAL BLOCK DIAGRAM

MUXOUT

CLK

DATA

LE

CE

PHASE

COMPARATOR

CHARGE

PUMP

OUTPUT

STAGE

OUTPUT

STAGE

MULTIPLEXER

10-BIT R

COUNTER

÷2

DIVIDER

×2

DOUBLER

FUNCTION

LATCH

DATA REGISTER

INTEGER

VALUE

N COUNTER

FRACTION

VALUE

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

MODULUS

VALUE

MULTIPLEXER

LOCK

DETECT

÷1/2/4/8/16/

32/64

ADF4356

VCO

CORE

Figure 1.