MOTOROLA CMOS LOGIC DATA

MC14580B

4

Figure 2. Power Dissipation Test Circuit and Waveforms (3–State Inputs are High)

PULSE

GENERATOR

1

PULSE

GENERATOR

2

PULSE

GENERATOR

3

VDD

IDD

WE

W0

W1

R0A

R1A

R0B

R1B

C

D0

D1

D2

D3

Q0A

Q1A

Q2A

Q3A

Q0B

Q1B

Q2B

Q3B

VSS

CL

CL

CL

CL

CL

CL

CL

CL

REPETITIVE WAVEFORMS

P.G. 1

P.G. 2

P.G. 3

OUTPUT

Qn A, B

Figure 3.

Figure 4.

CLOCK

ADDRESS DATA

Q

tw(H)

tw(L)

VDD

VSS

VDD

VSS

VOH

VOL

50%

tsu

th

50%

tPLH, tPHL

tTLH, tTHL

50%

90%

10%

3–STATE

A OR B

VDD

VSS

VOH

VOL

VOH

VOL

QA

QB

tPHZ

90%

50%

50%

10%

90%

10%

tPZL

tPZH

tPZL

CLOCK

WE

tsu

trem

50%

50%

50%

50%

VDD

VSS

VDD

VSS

DEVICE

UNDER

TEST

Q

CL

DEVICE

UNDER

TEST

Q

CL

1 k

Ω

CONNECT TO VCC WHEN TESTING tPLZ AND tPZL

CONNECT TO GND WHEN TESTING tPHZ AND tPZH

Figure 5.

Figure 6. Test Circuit

Figure 7. Test Circuit