MC145421

•MC145425

MOTOROLA

8

BACKGROUND

The MC145421 and the MC145425 ISDN UDLTs provide

an economical means of sending and receiving two B chan-

nels (64 kbps each) of voice/data and two D channels

(16 kbps each) of signal data in a two–wire configuration at

distances up to one kilometer. There are two ISDN UDLTs,

master and slave. The master UDLT is compatible with exist-

ing and evolving PABX architectures. This device transmits

2B+2D channels of data to the remote slave. At the remote

end, the slave device presents a replica of the PBX back-

plane to the terminal devices.

These devices permit existing digital PBX architectures to

remain unchanged and provide enhanced voice/data com-

munication services throughout the PBX service area by sim-

ply replacing a subscriber’s line card and telset.

All operations occur within the boundaries of an 8 kHz

frame (125

µs). In the master, the frame sequence begins on

the rising edge of MSI. In the slave, the frame begins after

the demodulation of a burst from the master. The slave initial-

izes its timing controls at this point to stay synchronized with

the master.

During one 125

µs frame four main activities are per-

formed:

1. Previously buffered 2B+2D channel data is burst to the

other end.

2. New 2B+2D channel data is accepted for the next

frame’s transmission.

3. An incoming burst is demodulated and stored.

4. 2B+2D channel data from the previous demodulated

frame is output.

The bursts are 20 bits long, composed of two 8–bit B chan-

nels and two 2–bit D channels. Bursts are encoded using a

modified DPSK method at 512 kHz. Since a single wire pair

is used, half–duplex operation is used. A 512 kHz burst is

sent from end to end in a ping–pong fashion. This method

provides apparent full–duplex 160 kbps transmission of data

at distances up to one kilometer.

GENERAL

The ISDN UDLT consists of a modulator, a demodulator,

intermediate data registers, receive and transmit data regis-

ters, and sequencing and control logic. The Rx and Tx buff-

ers interface digitally to the line card backplane signals, while

the modulator and demodulator interface to the twisted pair

transmission media. Intermediate data registers buffer data

between these main components. The ISDN UDLT is in-

tended to operate with a 5 V power supply and can be driven

by CMOS or TTL logic.

MASTER OPERATION

In the master, the rising edge of MSI initiates the 125

µs

frame. B channel data is clocked into the Rx registers under

control of TDC/RDC, RE1, and RE2. This data is combined

with the D channel data clocked in on pins D1I and D2I by the

DCLK. The resulting 20–bit packet is stored for the next

frame transmission to the slave UDLT.

The burst output to the slave consists of the 2B+2D data

loaded during the previous frame. The burst received from

the slave is demodulated and stored for outputting in the fol-

lowing frame.

B channel bits demodulated in the previous frame are out-

put on the Tx pin under control of TDC/RDC, TE1, and TE2.

Demodulated D channel bits are output on the D1O and D2O

output pins. The indication of a valid burst demodulation is

the VD output, which is updated at the start of every frame.

SLAVE OPERATION

In normal slave operation, the main synchronizing event is

completion of demodulating a burst from the master UDLT.

This action initializes the 125

µs frame boundary of the slave.

During the slave frame, B channel data is loaded and stored

under control of the BCLK, EN1, and EN2 outputs. D channel

data is loaded at D1I and D21 under control of the DCLK

output.

The demodulated burst from the master is separated into

its D channel and B channel components and output on the

D1O, D2O, and Tx pins. The return burst to the master con-

sisting of previously loaded 2B+2D data is transmitted eight

bauds after the completion of demodulation of the master’s

burst. This provides a period for line transients to diminish.

The start of the slave frame initiates two cycles of the

16 kHz DCLK, and one cycle each of the 8 kHz EN1 and EN2

enables. After completing their cycles, these outputs remain

low until another demodulation signals the start of a new

slave frame. In this manner, clock slip between the master

and slave UDLTs is absorbed each frame.

POWER–DOWN OPERATION

When PD is low in the master, the ISDN UDLT is powered

down and only that circuitry necessary to demodulate in-

coming bursts is active. No transmissions to the slave occur

during power down. If the master is receiving bursts from the

slave, the VD pin will change state upon completion of the

demodulation.

When the PD input pin is driven high, the master ISDN

UDLT is powered up. In this mode, the master bursts to the

slave every frame. B and D channel data can be loaded and

unloaded and VD is updated on the MSI rising edge.

If no bursts are received by the master, whether powered

up or not, the B channel data is unknown and the D channel

bits will remain at their last known values.

The PD pin on the slave UDLT is bidirectional with a weak

output driver that can be overdriven externally. When low,

either externally or internally derived, the slave is powered

down. No bursts to the master can be transmitted. EN1, EN2,

BCLK, and DCLK outputs are inactive during power down

except when TONE is high or a burst has been received from

the master. B and D channel data can be loaded and un-

loaded, and VD is updated upon completion of demodulation

of an incoming burst from the master. Input B and D channel

data is not transmitted until the slave is powered up, in which

case the first burst contains the most recently loaded data.

When the PD pin is high, the slave is powered up and

transmits every frame, the data enables and clocks are out-

put, and data can be loaded and unloaded.

TIME–OUT OPERATION

Time–out is an operating state in both the UDLT master

and slave devices. This state indicates that no incoming

bursts have been demodulated, forcing the VD pin low. An

internal counter is incremented for each frame that does not

contain an incoming burst. The counter is reset upon de-

modulating a burst from the far end. Time–out can occur

whether the device is powered up or down.