전자부품 데이터시트 검색엔진 |
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ADRF5020 데이터시트(PDF) 9 Page - Analog Devices |
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ADRF5020 데이터시트(HTML) 9 Page - Analog Devices |
9 / 12 page Data Sheet ADRF5020 Rev. A | Page 9 of 12 THEORY OF OPERATION The ADRF5020 requires a positive supply voltage applied to the VDD pin and a negative supply voltage applied to the VSS pin. Bypassing capacitors are recommended on the supply lines to minimize RF coupling. The ADRF5020 is internally matched to 50 Ω at the RF common port (RFC) and the RF throw ports (RF1 and RF2); therefore, no external matching components are required. All of the RF ports are dc-coupled to 0 V, and no dc blocking is required at the RF ports when the RF line potential is equal to 0 V. The design is bidirectional; the RF input signal can be applied to the RFC port while the RF throw port (RF1 or RF2) is output or vice versa. The ADRF5020 incorporates a driver to perform logic functions internally and to provide the user with the advantage of a simplified control interface. The driver features two digital control input pins, CTRL and EN. When the EN pin is logic low, the RF1 to RFC path is in an insertion loss state, and the RF2 to RFC path is in an isolation state, or vice versa, depending on the logic level applied to the CTRL pin. The insertion loss path (for example, RF1 to RFC) conducts the RF signal equally well in both directions between its throw port (for example, RF1) and common port (RFC). The isolation path (for example, RF2 to RFC) provides high loss between the insertion loss path and its throw port (for example, RF2) terminated to an internal 50 Ω resistor. When the EN pin is logic high, both the RF1 to RFC path and the RF2 to RFC path are in an isolation state regardless of the logic state of CTRL. RF1 and RF2 ports are terminated to internal 50 Ω resistors, and RFC becomes open reflective. The ideal power-up sequence is as follows: 1. Power up GND. 2. Power up VDD and VSS. The relative order is not important. 3. Power up the digital control inputs. The relative order of the logic control inputs is not important. However, powering the digital control inputs before the VDD supply can inadvertently forward bias and damage the internal ESD protection structures. 4. Apply an RF input signal. Table 4. Control Voltage Truth Table Digital Control Input RF Paths EN CTRL RF1 to RFC RF2 to RFC Low Low Isolation (off) Insertion loss (on) Low High Insertion loss (on) Isolation (off) High Low Isolation (off) Isolation (off) High High Isolation (off) Isolation (off) |
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