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AD5676R 데이터시트(PDF) 10 Page - Analog Devices |
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AD5676R 데이터시트(HTML) 10 Page - Analog Devices |
10 / 28 page Data Sheet AD5676 Rev. B | Page 9 of 27 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VOUT0 VDD VLOGIC SDI SCLK SYNC VOUT1 VOUT3 VREF RESET RSTSEL LDAC SDO VOUT6 VOUT7 GAIN VOUT5 VOUT4 GND VOUT2 TOP VIEW (Not to Scale) AD5676 Figure 5. 20-Lead TSSOP Pin Configuration Table 7. 20-Lead TSSOP Pin Function Descriptions Pin No. Mnemonic Description 1 VOUT1 Analog Output Voltage from DAC 1. The output amplifier has rail-to-rail operation. 2 VOUT0 Analog Output Voltage from DAC 0. The output amplifier has rail-to-rail operation. 3 VDD Power Supply Input. The AD5676 operates from 2.7 V to 5.5 V. Decouple VDD with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. 4 VLOGIC Digital Power Supply. Voltage ranges from 1.8 V to 5.5 V. 5 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, data transfers in on the falling edges of the next 24 clocks. 6 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data transfers at rates of up to 50 MHz. 7 SDI Serial Data Input. The AD5676 has a 24-bit input shift register. Data is clocked into the register on the falling edge of the serial clock input. 8 GAIN Span Set. When this pin is tied to GND, all eight DAC outputs have a span from 0 V to VREF. If this pin is tied to VLOGIC, all eight DACs output a span of 0 V to 2 × VREF. 9 VOUT7 Analog Output Voltage from DAC 7. The output amplifier has rail-to-rail operation. 10 VOUT6 Analog Output Voltage from DAC 6. The output amplifier has rail-to-rail operation. 11 VOUT5 Analog Output Voltage from DAC 5. The output amplifier has rail-to-rail operation. 12 VOUT4 Analog Output Voltage from DAC 4. The output amplifier has rail-to-rail operation. 13 GND Ground Reference Point for All Circuitry on the Device. 14 RSTSEL Power-On Reset. Tie this pin to GND to power up all eight DACs to zero scale. Tie this pin to VLOGIC to power up all eight DACs to midscale. 15 LDAC Load DAC. LDAC operates in two modes, asynchronously and synchronously. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs to update simultaneously. This pin can also be tied permanently low. 16 SDO Serial Data Output. Use this pin to daisy-chain a number of devices together, or use it for readback. The serial data transfers on the rising edge of SCLK and is valid on the falling edge. 17 RESET Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses are ignored. When RESET is activated, the input register and the DAC register are updated with zero scale or midscale, depending on the state of the RSTSEL pin. 18 VREF Reference Input Voltage. 19 VOUT3 Analog Output Voltage from DAC 3. The output amplifier has rail-to-rail operation. 20 VOUT2 Analog Output Voltage from DAC 2. The output amplifier has rail-to-rail operation. |
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