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AD5676BCPZ-REEL7 데이터시트(PDF) 5 Page - Analog Devices

부품명 AD5676BCPZ-REEL7
상세설명  Easy implementation
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AD5676
Data Sheet
Rev. B | Page 4 of 27
A Grade
B Grade
Test Conditions/Comments
Parameter
Min
Typ
Max
Min
Typ
Max
Unit
LOGIC INPUTS3
Input Current
±1
±1
µA
Per pin
Input Voltage
Low, VINL
0.3 ×
VLOGIC
0.3 ×
VLOGIC
V
High, VINH
0.7 ×
VLOGIC
0.7 ×
VLOGIC
V
Pin Capacitance
3
3
pF
LOGIC OUTPUTS (SDO)3
Output Voltage
Low, VOL
0.4
0.4
V
ISINK = 200 μA
High, VOH
VLOGIC
0.4
VLOGIC
0.4
V
ISOURCE = 200 μA
Floating State Output
Capacitance
4
4
pF
POWER REQUIREMENTS
VLOGIC
1.8
5.5
1.8
5.5
V
ILOGIC
3
3
µA
Power-on, −40°C to +105°C
3
3
µA
Power-on, −40°C to +125°C
3
3
µA
Power-down, −40°C to +105°C
3
3
µA
Power-down, −40°C to +125°C
VDD
2.7
5.5
2.7
5.5
V
Gain = 1
VREF +
1.5
5.5
VREF +
1.5
5.5
V
Gain = 2
IDD
Normal Mode7
1.1
1.26
1.1
1.26
mA
−40°C to +85°C
1.1
1.3
1.1
1.3
mA
−40°C to +105°C
All Power-Down Modes8
1
1.7
1
1.7
µA
Three-state, −40°C to +85°C
1
1.7
1
1.7
µA
Power down to 1 kΩ, −40°C to
+85°C
1
2.5
1
2.5
µA
Three-state, −40°C to +105°C
1
2.5
1
2.5
µA
Power down to 1 kΩ, −40°C to
+105°C
1
5.5
1
5.5
µA
Three-state, −40°C to +125°C
1
5.5
1
5.5
µA
Power down to 1 kΩ, −40°C to
+125°C
1
DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1 or when VREF/2 =
VDD with gain = 2. Linearity calculated using a reduced code range of 256 to 65,280.
2
See the Terminology section.
3
Guaranteed by design and characterization; not production tested.
4
Channel 0, Channel 1, Channel 2, and Channel 3 can together source/sink 40 mA. Similarly, Channel 4, Channel 5, Channel 6, and Channel 7 can together source/sink
40 mA up to a junction temperature of 125°C.
5
VDD = 5 V. The AD5676 includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded
during current limit. Operation above the specified maximum operation junction temperature may impair device reliability.
6
When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output
devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV.
7
Interface inactive. All DACs active. DAC outputs unloaded.
8
All DACs powered down.


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