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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SN74AUC2G32DCUR 데이터시트(PDF) 1 Page - Texas Instruments |
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SN74AUC2G32DCUR 데이터시트(HTML) 1 Page - Texas Instruments |
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1 / 10 page  SN74AUC2G32 DUAL 2INPUT POSITIVEOR GATE SCES478A − AUGUST 2003 − REVISED NOVEMBER 2003 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Available in the Texas Instruments NanoStar and NanoFree Packages D Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation D Ioff Supports Partial-Power-Down Mode Operation D Sub 1-V Operable D Max tpd of 1.5 ns at 1.8 V D Low Power Consumption, 10 µA at 1.8 V D ±8-mA Output Drive at 1.8 V D Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) description/ordering information This dual 2-input positive-OR gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC2G32 performs the Boolean function Y + A ) Bor Y + A • B in positive logic. NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. For more information about AUC Little Logic devices, please refer to the TI application report, Applications of Texas Instruments AUC Sub-1-V Little Logic Devices, literature number SCEA027. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING‡ NanoStar − WCSP (DSBGA) 0.23-mm Large Bump − YEP Tape and reel SN74AUC2G32YEPR _ _ _UG_ −40 °C to 85°C NanoFree − WCSP (DSBGA) 0.23-mm Large Bump − YZP (Pb-free) Tape and reel SN74AUC2G32YZPR _ _ _UG_ SSOP − DCT Tape and reel SN74AUC2G32DCTR U32_ _ _ VSSOP − DCU Tape and reel SN74AUC2G32DCUR U32_ † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site. DCU: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). Copyright 2003, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DCT OR DCU PACKAGE (TOP VIEW) 1 2 3 4 8 7 6 5 1A 1B 2Y GND VCC 1Y 2B 2A 4 3 2 1 5 6 7 8 GND 2Y 1B 1A 2A 2B 1Y VCC YEP OR YZP PACKAGE (BOTTOM VIEW) NanoStar and NanoFree are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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