ADV7189KST datasheet(11/104 Pages) AD

부품명	ADV7189KST

상세설명	Multiformat SDTV Video Decoder

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ADV7189

Rev. A | Page 11 of 104

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

VS

1

HS

2

DGND

3

DVDDIO

4

P15

5

P14

6

P13

7

P12

8

DGND

9

DVDD 10

NC 11

SFL 12

NC 13

DGND 14

DVDDIO 15

NC 16

P11 17

P10 18

P9 19

P8 20

AIN5

60

AIN11

59

AIN4

58

AIN10

57

AGND

56

CAP C2

55

CAP C1

54

AGND

53

CML

52

REFOUT

51

AVDD

50

CAP Y2

49

CAP Y1

48

AGND

47

AIN3

46

AIN9

45

AIN2

44

AIN8

43

AIN1

42

AIN7

41

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

ADV7189

TOP VIEW

(Not to Scale)

NC = NO CONNECT

Figure 5. 80-Lead LQFP Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Type

Function

3, 9, 14, 31, 71

DGND

G

Digital Ground.

39, 40, 47, 53,

56

AGND

G

Analog Ground.

4, 15

DVDDIO

P

Digital I/O Supply Voltage (3.3 V).

10, 30, 72

DVDD

P

Digital Core Supply Voltage (1.8 V).

50

AVDD

P

Analog Supply Voltage (3.3 V).

38

PVDD

P

PLL Supply Voltage (1.8 V).

41–46, 57–62

AIN1–AIN12

I

Analog Video Input Channels.

11, 13, 16, 25,

63, 65, 69, 70,

77, 78

NC

No Connect Pins.

5–8, 17–24,

32–35, 73–76

P0–P19

O

Video Pixel Output Port.

2

HS

O

HS is a horizontal synchronization output signal.

1

VS

O

VS is a vertical synchronization output signal.

80

FIELD

O

FIELD is a field synchronization output signal.

67

SDA

I/O

I2C Port Serial Data Input/Output Pin.

68

SCLK

I

I2C Port Serial Clock Input (Max Clock Rate of 400 kHz).

66

ALSB

I

This pin selects the I2C address for the ADV7189. ALSB set to a Logic 0 sets the address for a

write as 0x40; for ALSB set to a logic high, the address selected is 0x42.

64

RESET

I

System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to reset

the ADV7189 circuitry.

27

LLC1

O

This is a line-locked output clock for the pixel data output by the ADV7189. Nominally 27 MHz,

but varies up or down according to video line length.

26

LLC2

O

This is a divide-by-2 version of the LLC1 output clock for the pixel data output by the ADV7189.

Nominally 13.5 MHz, but varies up or down according to video line length.

유사한 부품 번호 - ADV7189KST

제조업체	부품명	데이터시트	상세설명
Analog Devices	ADV7189B	880Kb / 104P	Multiformat SDTV Video Decoder REV. B
	ADV7189B	783Kb / 104P	Multiformat SDTV Video Decoder REV. B
	ADV7189B	881Kb / 104P	Multiformat SDTV Video Decoder REV. B
	ADV7189BBSTZ268H	880Kb / 104P	Multiformat SDTV Video Decoder REV. B
	ADV7189BBSTZ268H2	783Kb / 104P	Multiformat SDTV Video Decoder REV. B

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유사한 설명 - ADV7189KST

제조업체	부품명	데이터시트	상세설명
Analog Devices	ADV7181	833Kb / 104P	Multiformat SDTV Video Decoder Rev. B
	ADV7189B	880Kb / 104P	Multiformat SDTV Video Decoder REV. B
	ADV7183B	912Kb / 100P	Multiformat SDTV Video Decoder Rev. B
	ADV7189B	881Kb / 104P	Multiformat SDTV Video Decoder REV. B
	ADV7181B	2Mb / 100P	Multiformat SDTV Video Decoder Rev. B
	ADV7183A	850Kb / 104P	Multiformat SDTV Video Decoder Rev. B
	ADV7189	3Mb / 104P	Multiformat SDTV Video Decoder REV. B
	ADV7181	884Kb / 96P	Multiformat SDTV Video Decoder REV. 0
	ADV7183A	894Kb / 104P	Multiformat SDTV Video Decoder REV. A
	ADV7183B	911Kb / 100P	Multiformat SDTV Video Decoder REV. B

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유사한 부품 번호 - ADV7189KST

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