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TSB43CA43AZGW 데이터시트(PDF) 6 Page - Texas Instruments |
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TSB43CA43AZGW 데이터시트(HTML) 6 Page - Texas Instruments |
6 / 97 page TSB43Cx43A/ TI iceLynx-Micro™ IEEE 1394a-2000 TSB43CA42 Consumer Electronics Solution TEXAS INSTRUMENTS SLLS546F – March 2004 – Revised September 2004 PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TEXAS INSTRUMENTS Copyright 2004, Texas Instruments Incorporated MARCH 12, 2004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 6 List Of Tables Table 1. External CPU MCIF Pin Assignment Modes ................................................................................28 Table 2. Ex-CPU I/F Signals ....................................................................................................................... 29 Table 3. Ex-CPU Access Limitation ............................................................................................................ 32 Table 4. I/O Type-0 68K + Wait Read MCIF AC-Timing Parameters ......................................................... 34 Table 5. I/O Type-0 68K + Wait Write MCIF AC Timing Parameters ......................................................... 36 Table 6. I/O Type-1 SH3 Critical Timing (Read) ......................................................................................... 38 Table 7. I/O Type-1 SH3 AC Timing (Write) ............................................................................................... 40 Table 8. I/O Type-2 M16C SRAM-Like + Wait AC Timing Parameters (Read) .......................................... 42 Table 9. I/O Type-2 M16C SRAM-Like + Wait AC Timing Parameters (Write) .......................................... 44 Table 10. I/O Type-3 MPC850 Read AC Timing Parameters..................................................................... 46 Table 11. I/O Type-3 MPC850 Write AC Timing Parameters ..................................................................... 48 Table 12. Memory Type Read AC Timing Parameters............................................................................... 50 Table 13. Memory Type Write AC Timing Parameters ...............................................................................52 Table 14. Ex-CPU Encryption First Quadlet ............................................................................................... 52 Table 15. Ex-CPU Encryption Reference ................................................................................................... 53 Table 16. HSDI Signals............................................................................................................................... 55 Table 17. Application Counter Values......................................................................................................... 56 Table 18. HSDI Pass-Through Function ..................................................................................................... 57 Table 19. HSDI Maximum Clock Rates and Throughput............................................................................ 57 Table 20. General HSDI Mode Settings...................................................................................................... 58 Table 21. HSDI Video Modes ..................................................................................................................... 59 Table 22. AC Timing Parameters for Serial I/F (Modes 1 and 4)................................................................ 64 Table 23. AC Timing Parameters for Serial I/F (Modes 2 and 3)................................................................ 64 Table 24. AC Timing Parameters for Parallel I/F (Modes 5, 6, and 7)........................................................ 65 Table 25. AC Timing Parameters for Parallel I/F (Modes 8 and 9)............................................................. 65 Table 26. AC Timing Parameters for Serial I/F (Mode 1) ........................................................................... 65 Table 27. AC Timing Parameters for Parallel I/F (Mode 2)......................................................................... 65 Table 28. AC Timing Parameters for Parallel I/F (Modes 3 and 4)............................................................. 66 Table 29. HSDI0 DVD Audio Signals.......................................................................................................... 66 Table 30. HSDI1 DVD-Audio Signals.......................................................................................................... 66 Table 31. AC Timing Parameters................................................................................................................ 68 Table 32. AC Timing Parameters................................................................................................................ 69 Table 33. AC Timing Parameters................................................................................................................ 70 Table 34. UART CFR Address Offsets ....................................................................................................... 70 Table 35. UART Registers .......................................................................................................................... 71 Table 36. PHY Access Register.................................................................................................................. 72 Table 37. Base Register Configuration ....................................................................................................... 73 Table 38. Base Register Field Descriptions................................................................................................ 73 Table 39. Page 0 (Port Status) Register Configuration .............................................................................. 76 Table 40. Page 0 (Port Status) Register Field Descriptions ....................................................................... 76 Table 41. Page 1 (Vendor ID) Register Configuration ................................................................................ 77 Table 42. Page 1 (Vendor ID) Register Field Descriptions......................................................................... 77 Table 43. Power State Summary ................................................................................................................ 79 Table 44. I/O Pin and CFR Descriptions for Controlling Power Management States................................. 82 Table 45. FIFO Monitoring Bits ................................................................................................................... 85 Table 46. Summary of GPIO Use ............................................................................................................... 86 Table 47. CFR Address Ranges ................................................................................................................. 88 Table 48. Pin State During Power On Reset, Just After Power On Reset and DISABLE_IFn=L............... 94 |
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