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REF_IN

VIDSEL

AUDSEL

MCSEL

MUX

VIDCLK

AUDCLK

PLL1VSS

PLL1VDD

PLL2VDD

PLL3VDD

PLL2VSS

PLL3VSS

MUX

CPUCLK

ASICCLK

USBCLK

MCCLK

/4

/6

/3

/5

/10

PLL 2

12.288/16.9344 MHz

PLL 3

192 MHz

PLL3VDD

PLL 1

74.175824 MHz

/16

100 k

Ω

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

100 k

Ω

100 k

Ω

100 k

Ω

100 k

Ω

100 k

Ω

Power

Down

Logic

CDC5806

SCAS760A – MARCH 2004 – REVISED JULY 2004

These devices have limited built-in ESD protection. The leads should be shorted together or the device

placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

FUNCTIONAL BLOCK DIAGRAM

2