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CD54ACT00F3A 데이터시트(PDF) 4 Page - Texas Instruments |
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CD54ACT00F3A 데이터시트(HTML) 4 Page - Texas Instruments |
4 / 5 page CD54ACT00, CD74ACT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCHS308B – JANUARY 2001 – REVISED JUNE 2002 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES th tsu 10% 10% 90% 90% 3 V 3 V 0 V 0 V tr tf Reference Input Data Input VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES 50% VCC 50% 10% 10% 90% 90% 3 V VOH VOL 0 V tr tf Input In-Phase Output tPLH tPHL 50% VCC 50% 10% 10% 90% 90% VOH VOL tr tf tPHL tPLH Out-of-Phase Output NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. Phase relationships between waveforms are arbitrary. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLH and tPHL are the same as tpd. G. tPZL and tPZH are the same as ten. H. tPLZ and tPHZ are the same as tdis. From Output Under Test CL = 50 pF (see Note A) LOAD CIRCUIT S1 2 × VCC R1 = 500 Ω Open GND 0 V tw VOLTAGE WAVEFORMS PULSE DURATION Input 3 V tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND TEST S1 Output Control Output Waveform 1 S1 at 2 × VCC (see Note B) Output Waveform 2 S1 at GND (see Note B) VOL VOH tPZL tPZH tPLZ tPHZ ≈VCC 0 V 20% VCC 20% VCC 80% VCC ≈0 V VOLTAGE WAVEFORMS OUTPUT ENABLE AND DISABLE TIMES 80% VCC 3 V R2 = 500 Ω VOLTAGE WAVEFORMS RECOVERY TIME 3 V 0 V CLR Input CLK 3 V trec 0 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V Figure 1. Load Circuit and Voltage Waveforms |
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