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MT18VDDT12872AG 데이터시트(PDF) 13 Page - Micron Technology |
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MT18VDDT12872AG 데이터시트(HTML) 13 Page - Micron Technology |
13 / 29 page 256MB, 512MB, 1GB (x72, ECC, DR), PC3200 184-PIN DDR SDRAM UDIMM pdf: 09005aef80814e61, source: 09005aef80a43eed Micron Technology, Inc., reserves the right to change products or specifications without notice. DDA18C32_64_128x72AG.fm - Rev. E 9/04 EN 13 ©2004 Micron Technology, Inc. Table 12: IDD Specifications and Conditions – 256MB DDR SDRAM components only Notes: 1–5, 8, 10, 12; notes appear on pages 19–21; 0°C ≤ T A ≤ +70°C; VDD = VDDQ = +2.6V ±0.1V MAX PARAMETER/CONDITION SYM -40B UNITS NOTES OPERATING CURRENT: One device bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles IDD0a 1,062 mA 21, 41 OPERATING CURRENT: One device bank; Active -Read Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle IDD1a 1,242 mA 21, 41 PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDD2Pb 27 mA 21, 28, 43 IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK = tCK MIN; CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM IDD2Fb 450 mA 44 ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW IDD3Pb 225 mA 21, 28, 43 ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle IDD3Nb 450 mA OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA IDD4Ra 1,242 mA 21, 41 OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle IDD4Wa 1,422 mA 21 AUTO REFRESH CURRENT tREFC = tRFC (MIN) IDD5b 2,160 mA 43 tREFC = 15.625µs IDD5Ab 54 mA 24, 43 SELF REFRESH CURRENT: CKE ≤ 0.2V IDD6b 36 mA 9 OPERATING CURRENT: Four device bank interleaving READs (BL = 4) with auto precharge, tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during Active READ, or WRITE commands IDD7a 3,222 mA 20, 42 NOTE: a: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode. b: Value calculated reflects all module ranks in this operating condition. |
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