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AM29LV065DU121REIN 데이터시트(PDF) 4 Page - Advanced Micro Devices |
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4 / 52 page January 10, 2002 Am29LV065D 3 TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9 Table 1. Am29LV065D Device Bus Operations ................................9 VersatileIO TM (V IO) Control ........................................................ 9 Requirements for Reading Array Data ..................................... 9 Writing Commands/Command Sequences ............................ 10 Accelerated Program Operation ............................................. 10 Autoselect Functions .............................................................. 10 Standby Mode ........................................................................ 10 Automatic Sleep Mode ........................................................... 10 RESET#: Hardware Reset Pin ............................................... 10 Output Disable Mode .............................................................. 11 Table 2. Sector Address Table ........................................................11 Autoselect Mode ..................................................................... 15 Table 3. Am29LV065D Autoselect Codes, (High Voltage Method) 15 Sector Group Protection and Unprotection ............................. 16 Table 4. Sector Group Protection/Unprotection Address Table .....16 Temporary Sector Group Unprotect ....................................... 17 Figure 1. Temporary Sector Group Unprotect Operation................ 17 Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 18 SecSi (Secured Silicon) Sector Flash Memory Region .......... 19 Table 5. SecSi Sector Contents ......................................................19 Hardware Data Protection ...................................................... 19 Low VCC Write Inhibit ............................................................ 19 Write Pulse “Glitch” Protection ............................................... 20 Logical Inhibit .......................................................................... 20 Power-Up Write Inhibit ............................................................ 20 Common Flash Memory Interface (CFI) . . . . . . . 20 Table 6. CFI Query Identification String .......................................... 20 System Interface String................................................................... 21 Table 8. Device Geometry Definition .............................................. 21 Table 9. Primary Vendor-Specific Extended Query ........................ 22 Command Definitions . . . . . . . . . . . . . . . . . . . . . 22 Reading Array Data ................................................................ 22 Reset Command ..................................................................... 23 Autoselect Command Sequence ............................................ 23 Enter SecSi Sector/Exit SecSi Sector Command Sequence .............................................................. 23 Byte Program Command Sequence ....................................... 23 Unlock Bypass Command Sequence ..................................... 24 Figure 3. Program Operation .......................................................... 24 Chip Erase Command Sequence ........................................... 24 Sector Erase Command Sequence ........................................ 25 Erase Suspend/Erase Resume Commands ........................... 25 Figure 4. Erase Operation............................................................... 26 Command Definitions ............................................................. 27 Table 10. Am29LV065D Command Definitions ..............................27 Write Operation Status . . . . . . . . . . . . . . . . . . . . . 28 DQ7: Data# Polling ................................................................. 28 Figure 5. Data# Polling Algorithm ................................................... 28 RY/BY#: Ready/Busy# ........................................................... 29 DQ6: Toggle Bit I .................................................................... 29 Figure 6. Toggle Bit Algorithm........................................................ 29 DQ2: Toggle Bit II ................................................................... 30 Reading Toggle Bits DQ6/DQ2 ............................................... 30 DQ5: Exceeded Timing Limits ................................................ 30 DQ3: Sector Erase Timer ....................................................... 30 Table 11. Write Operation Status ................................................... 31 Absolute Maximum Ratings . . . . . . . . . . . . . . . . 32 Figure 7. Maximum Negative Overshoot Waveform ..................... 32 Figure 8. Maximum Positive Overshoot Waveform....................... 32 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 32 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) ............................................................. 34 Figure 10. Typical I CC1 vs. Frequency ............................................ 34 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 11. Test Setup.................................................................... 35 Table 12. Test Specifications ......................................................... 35 Figure 12. Input Waveforms and Measurement Levels ................. 35 Key to Switching Waveforms. . . . . . . . . . . . . . . . 35 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 36 Read-Only Operations ........................................................... 36 Figure 13. Read Operation Timings ............................................... 36 Hardware Reset (RESET#) .................................................... 37 Figure 14. Reset Timings ............................................................... 37 Erase and Program Operations .............................................. 38 Figure 15. Program Operation Timings.......................................... 39 Figure 16. Accelerated Program Timing Diagram.......................... 39 Figure 17. Chip/Sector Erase Operation Timings .......................... 40 Figure 18. Data# Polling Timings (During Embedded Algorithms). 41 Figure 19. Toggle Bit Timings (During Embedded Algorithms)...... 42 Figure 20. DQ2 vs. DQ6................................................................. 42 Temporary Sector Unprotect .................................................. 43 Figure 21. Temporary Sector Group Unprotect Timing Diagram ... 43 Figure 22. Sector Group Protect and Unprotect Timing Diagram .. 44 Figure 23. Alternate CE# Controlled Write (Erase/Program) Operation Timings .............................................. 46 Erase And Programming Performance . . . . . . . 47 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 47 TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 47 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 48 TS 048—48-Pin Standard Pinout Thin Small Outline Package (TSOP) ..................................................................... 48 TSR048—48-Pin Reverse Pinout Thin Small Outline Package (TSOP) ..................................................................... 49 FBE063—63-Ball Fine-Pitch Ball Grid Array (FBGA) 11 x 12 mm package .............................................................. 50 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 51 Revision A (July 27, 2000) ...................................................... 51 Revision A+1 (August 4, 2000) ............................................... 51 Revision A+2 (August 14, 2000) ............................................. 51 Revision A+3 (August 25, 2000) ............................................. 51 Revision A+4 (October 19, 2000) ........................................... 51 Revision A+5 (November 7, 2000) ......................................... 51 Revision A+6 (November 27, 2000) ....................................... 51 Revision A+7 (March 8, 2001) ................................................ 51 Revision B (January 10, 2002) ............................................... 51 |
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