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CDCM1804RGERG4 데이터시트(PDF) 7 Page - Texas Instruments

부품명 CDCM1804RGERG4
상세설명  1:3 LVPECL CLOCK BUFFER ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER
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LVCMOS OUTPUT PARAMETER, Y3
JITTER CHARACTERISTICS
CDCM1804
SCAS697E – JULY 2003 – REVISED MAY 2005
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fclk
OUTPUT frequency, see Figure 5(1).
0
200
MHz
Output skew between the LVCMOS out-
tskLVCMOS(o)
VOX to VDD/2, see Figure 8.
1.3
1.6
2.1
ns
put Y3 and LVPECL outputs Y[2:0]
tsk(pp)
Part-to-part skew
Y3, see Note B in Figure 8.
300
ps
VDD = min to max
IOH = –100 µA
VDD – 0.1
VOH
High-level output voltage
VDD = 3 V
IOH = –6 mA
2.4
V
VDD = 3 V
IOH = –12 mA
2
VDD = min to max
IOL = 100 µA
0.1
VOL
Low-level output voltage
VDD = 3 V
IOL = 6 mA
0.5
V
VDD = 3 V
IOL = 12 mA
0.8
IOH
High-level output current
VDD = 3.3 V
VO = 1.65 V
–29
mA
IOL
Low-level output current
VDD = 3.3 V
VO = 1.65 V
37
mA
IOZ
High-impedance-state output current
VDD = 3.6 V
VO = VDD or 0 V
±5
µA
CO
Output capacitance
VDD = 3.3 V
2
pF
tDuty
Output duty cycle distortion(2)
Measured at VDD/2
–150
150
ps
Propagation delay rising edge from IN to
tpd(lh)
VOX to VDD/2 load, see Figure 10.
1.6
2.6
ns
Y3
Propagation delay falling edge from IN
tpd(hl)
VOX to VDD/2 load, see Figure 10.
1.6
2.6
ns
to Y3
tr
Output rise slew rate
20% to 80% of swing, see Figure 10.
1.4
2.3
V/ns
tf
Output fall slew rate
80% to 20% of swing, see Figure 10.
1.4
2.3
V/ns
(1)
Operating the CDCM1804 LVCMOS output above the maximum frequency does not cause a malfunction to the device, but the Y3
output will not achieve enough signal swing to meet the output specification. Therefore, the CDCM1804 can be operated at higher
frequencies, while the LVCMOS output Y3 becomes unusable.
(2)
For a 200-MHz signal, the 150-ps error would result in a duty cycle distortion of
±3% when driven by an ideal clock input signal.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
12 kHz to 20 MHz,
fout = 250 MHz to 800 MHz,
0.15
divide-by-1 mode
Additive phase jitter from input to
tjitterLVPECL
ps rms
LVPECL output Y[2:0], see Figure 2. 50 kHz to 40 MHz,
fout = 250 MHz to 800 MHz,
0.25
divide-by-1 mode
12 kHz to 20 MHz, fout = 250 MHz,
0.25
divide-by-1 mode
Additive phase jitter from input to
tjitterLVCMOS
ps rms
LVCMOS output Y3, see Figure 3.
50 kHz to 40 MHz, fout = 250 MHz,
0.4
divide-by-1 mode
7


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