CDCM1804RGERG4 datasheet(10/27 Pages) TI1

부품명	CDCM1804RGERG4

상세설명	1:3 LVPECL CLOCK BUFFER ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER

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제조업체	TI1 [Texas Instruments]

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PACKAGE THERMAL RESISTANCE

CONTROL INPUT CHARACTERISTICS

BIAS VOLTAGE VBB

CDCM1804

SCAS697E – JULY 2003 – REVISED MAY 2005

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

QFN-24 package thermal resistance(1)

4-layer JEDEC test board (JESD51-7),

RθJA-1

106.6

°C/W

airflow = 0 ft/min

QFN-24 package thermal resistance

4-layer JEDEC test board (JESD51-7) with four

RθJA-2 with thermal vias in PCB

(1)

thermal vias of 22-mil diameter each,

55.4

°C/W

airflow = 0 ft/min

(1)

It is recommended to provide four thermal vias to connect the thermal pad of the package effectively with the PCB and ensure a good

heat sink.

Example:

Calculation of the junction-lead temperature with a 4-layer JEDEC test board using four thermal vias:

TChassis = 85°C (temperature of the chassis)

Peffective = Imax × Vmax = 110 mA × 3.6 V = 396 mW (maximum power consumption inside the package)

θT

Junction = R

θJA-2 × Peffective = 55.45°C/W × 396 mW = 21.96°C

TJunction = θTJunction + TChassis = 21.96°C + 85°C = 107°C (the maximum junction temperature of

Tdie-max = 125°C is not violated)

over recommended operating free-air temperature range

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tsu

Setup time, S0, S1, S2, and EN terminals before clock IN

25

ns

th

Hold time, S0, S1, S2, and EN terminals after clock IN

0

ns

Time between latching the EN low transition and when all

t(disable)

outputs are disabled (how much time is required until the

10

ns

outputs turn off)

Time between latching the EN low-to-high transition and when

t(enable)

outputs are enabled based on control settings (how much time

1

µs

passes before the outputs carry valid signals)

Rpullup

Internal pullup resistor on S[2:0] and EN inputs

42

60

78

k

Ω

VIH(H)

Three-level input high, S0, S1, S2, and EN terminals(1)

0.9 VDD

V

VIM(M)

Three-level input MID, S0, S1, S2, and EN terminals

0.3 VDD

0.7 VDD

V

VIL(L)

Three-level input low, S0, S1, S2, and EN terminals

0.1 VDD

V

IIH

VI = VDD

–5

µA

Input current, S0, S1, S2, and EN terminals

IIL

VI = GND

38

85

µA

(1)

Leaving this terminal floating automatically pulls the logic level high to VDD through an internal pullup resistor of 60 kΩ.

over recommended operating free-air temperature range

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VBB

Output reference voltage

VDD = 3 V–3.6 V, IBB = –0.2 mA

VDD – 1.4

VDD – 1.2

V

10

유사한 부품 번호 - CDCM1804RGERG4

제조업체	부품명	데이터시트	상세설명
Texas Instruments	CDCM1804RGERG4	589Kb / 24P	[Old version datasheet] 1:3 LVPECL CLOCK BUFFER ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER

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제조업체	부품명	데이터시트	상세설명
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CDCM1804RGERG4 데이터시트(PDF) 10 Page - Texas Instruments

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유사한 부품 번호 - CDCM1804RGERG4

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