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CDCE937 데이터시트(PDF) 6 Page - Texas Instruments |
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CDCE937 데이터시트(HTML) 6 Page - Texas Instruments |
6 / 39 page 6 CDCE937, CDCEL937 SLAS564G – AUGUST 2007 – REVISED OCTOBER 2016 www.ti.com Product Folder Links: CDCE937 CDCEL937 Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated Recommended Operating Conditions (continued) MIN NOM MAX UNIT CL On-chip load capacitance at Xin and Xout 0 20 pF (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.4 Thermal Information THERMAL METRIC(1) CDCE937, CDCEL937 UNIT PW (TSSOP) 20 PINS RθJA Junction-to-ambient thermal resistance 89.04 °C/W RθJC(top) Junction-to-case (top) thermal resistance 31.33 °C/W RθJB Junction-to-board thermal resistance 54.6 °C/W ψJT Junction-to-top characterization parameter 0.8 °C/W ψJB Junction-to-board characterization parameter 48.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — °C/W (1) All typical values are at respective nominal VDD. 6.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT IDD Supply current (see Figure 1) All outputs off, f(CLK) = 27 MHz, f(VCO) = 135 MHz All PLLS on 29 mA Per PLL 9 IDDOUT Output supply current (see Figure 2 and Figure 3) No load, all outputs on, fOUT = 27 MHz CDCE937, VDDOUT = 3.3 V 3.1 mA CDCEL937, VDDOUT = 1.8 V 1.5 IDD(PD) Power-down current Every circuit powered down except SDA/SCL, fIN = 0 MHz, VDD = 1.9 V 50 µA V(PUC) Supply voltage Vdd threshold for power- up control circuit 0.85 1.45 V f(VCO) VCO frequency range of PLL 80 230 MHz fOUT LVCMOS output frequency Vddout = 3.3 V 230 MHz Vddout = 1.8 V 230 LVCMOS PARAMETER VIK LVCMOS input voltage VDD = 1.7 V, II = –18 mA –1.2 V II LVCMOS Input current VI = 0 V or VDD, VDD = 1.9 V ±5 µA IIH LVCMOS Input current for S0/S1/S2 VI = VDD, VDD = 1.9 V 5 µA IIL LVCMOS Input current for S0/S1/S2 VI = 0 V, VDD = 1.9 V –4 µA CI Input capacitance at Xin/Clk VI(Clk) = 0 V or VDD 6 pF Input capacitance at Xout VI(Xout) = 0 V or VDD 2 Input capacitance at S0/S1/S2 VIS = 0 V or VDD 3 CDCE937 – LVCMOS FOR Vddout = 3.3 V VOH LVCMOS high-level output voltage Vddout = 3 V, IOH = –0.1 mA 2.9 V Vddout = 3 V, IOH = –8 mA 2.4 Vddout = 3 V, IOH = –12 mA 2.2 VOL LVCMOS low-level output voltage Vddout = 3 V, IOL = 0.1 mA 0.1 V Vddout = 3 V, IOL = 8 mA 0.5 Vddout = 3 V, IOL = 12 mA 0.8 tPLH, tPHL Propagation delay All PLL bypass 3.2 ns tr/tf Rise and fall time Vddout = 3.3 V (20%–80%) 0.6 ns |
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