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Si4731-C40-GM 데이터시트(PDF) 10 Page - Silicon Laboratories |
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Si4731-C40-GM 데이터시트(HTML) 10 Page - Silicon Laboratories |
10 / 42 page Si4730/31-C40 10 Rev. 1.0 Figure 6. SPI Control Interface Write Timing Parameters Figure 7. SPI Control Interface Read Timing Parameters Table 7. SPI Control Interface Characteristics (VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit SCLK Frequency fCLK 0— 2.5 MHz SCLK High Time tHIGH 25 — — ns SCLK Low Time tLOW 25 — — ns SDIO Input, SEN to SCLK Setup tS 15 — — ns SDIO Input to SCLK Hold tHSDIO 10 — — ns SEN Input to SCLK Hold tHSEN 5— — ns SCLK to SDIO Output Valid tCDV Read 2 — 25 ns SCLK to SDIO Output High Z tCDZ Read 2 — 25 ns SCLK, SEN, SDIO, Rise/Fall time tR, tF — — 10 ns Note: When selecting SPI mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the rising edge of RST. SCLK 70% 30% SEN 70% 30% SDIO C7 C0 70% 30% tS C6–C1 Control Byte In 8 Data Bytes In D7 D6–D1 D0 tS tHSDIO tHIGH tLOW tHSEN tF tR Bus Turnaround SCLK 70% 30% SEN 70% 30% SDIO 70% 30% tHSDIO Control Byte In C7 C0 C6–C1 tS tHSEN tS tCDZ tCDV 16 Data Bytes Out (SDIO or GPO1) D7 D6–D1 D0 |
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