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TLV320AIC3262 데이터시트(PDF) 58 Page - Texas Instruments

부품명 TLV320AIC3262
상세설명  Ultralow Power Stereo Audio Codec With miniDSP, DirectPath Headphone, and Stereo Class-D Speaker Amplifier
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TLV320AIC3262
SLAS679A – DECEMBER 2011 – REVISED SEPTEMBER 2015
www.ti.com
portable audio system, hardware design of the audio system is greatly simplified. In addition to these three
individual digital audio interfaces, a fourth set of digital audio pins can be muxed into Audio Serial Interface 1. In
other words, four separate 4-wire digital audio buses can be connected to the TLV320AIC3262. However, it
should be noted that only one of the three audio serial interfaces can be routed to/from the DACs/ADCs at a
time.
Each audio bus on the TLV320AIC3262 is very flexible, including left or right-justified data options, support for
I2S or PCM protocols, programmable data length options, a TDM mode for multichannel operation, very flexible
master or slave configurability for each bus clock line, and the ability to communicate with multiple devices within
a system directly. Each of the three audio buses of the TLV320AIC3262 can be configured for left or right-
justified, I2S, DSP, or TDM modes of operation, where communication with PCM interfaces is supported within
the TDM mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits. In
addition, the word clock and bit clock can be independently configured in either Master or Slave mode, for
flexible connectivity to a wide variety of processors. The word clock is used to define the beginning of a frame,
and may be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to
the maximum of the selected ADC and DAC sampling frequencies. When configuring an audio interface for six-
wire mode, the ADC and DAC paths can operate based on separate word clocks. The bit clock is used to clock
in and clock out the digital audio data across the serial bus. When in Master mode, this signal can be
programmed to generate variable clock pulses by controlling the bit-clock divider. The number of bit-clock pulses
in a frame may need adjustment to accommodate various word-lengths as well as to support the case when
multiple TLV320AIC3262s may share the same audio bus. When configuring an audio interface for six-wire
mode, the ADC and DAC paths can operate based on separate bit clocks. The TLV320AIC3262 also includes a
feature to offset the position of start of data transfer with respect to the word-clock. This offset can be controlled
in terms of number of bit-clocks. The TLV320AIC3262 also has the feature of inverting the polarity of the bit-clock
used for transferring the audio data as compared to the default clock polarity used. This feature can be used
independently of the mode of audio interface chosen. The TLV320AIC3262 further includes programmability to 3-
state the DOUT line during all bit clocks when valid data is not being sent. By combining this capability with the
ability to program at what bit clock in a frame the audio data begins, time-division multiplexing (TDM) can be
accomplished, enabling the use of multiple codecs on a single audio serial data bus. When the audio serial data
bus is powered down while configured in master mode, the pins associated with the interface are put into a 3-
state output condition.
By default, when the word-clocks and bit-clocks are generated by the TLV320AIC3262, these clocks are active
only when the codec (ADC, DAC or both) are powered up within the device. This is done to save power.
However, it also supports a feature when both the word clocks and bit-clocks can be active even when the codec
is powered down. This is useful when using the TDM mode with multiple codecs on the same bus, or when
wordclock or bit-clocks are used in the system as general-purpose clocks.
For more detailed information see the TLV320AIC3262 Applications Reference Guide, SLAU309.
58
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유사한 설명 - TLV320AIC3262_17

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