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TDA1MDRCCYEA0 데이터시트(PDF) 98 Page - Texas Instruments |
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TDA1MDRCCYEA0 데이터시트(HTML) 98 Page - Texas Instruments |
98 / 377 page TMS320DM8148, TMS320DM8147 SPRS647E – MARCH 2011 – REVISED DECEMBER 2013 www.ti.com 3.2.11 McASP Table 3-17. McASP0 Terminal Functions SIGNAL TYPE(1) OTHER(2) (3) MUXED DESCRIPTION NAME NO. McASP0 MCA[5] MCA[0]_ACLKR/ IPD K2 I/O PINCNTL19 McASP0 Receive Bit Clock I/O MCA[5]_AXR[2] DVDD DSIS: 0 MCA[5] MCA[0]_AFSR/ IPD K1 I/O PINCNTL20 McASP0 Receive Frame Sync I/O MCA[5]_AXR[3] DVDD DSIS: 0 IPD – MCA[0]_ACLKX R4 I/O McASP0 Transmit Bit Clock I/O DVDD PINCNTL17 AUD_CLKIN0/ AUD_CLKIN0, MCA[0]_AXR[7]/ MCA[0], MCA[3], IPD MCA[0]_AHCLKX/ L5 I/O USB1 McASP0 Transmit High-Frequency Master Clock I/O DVDD MCA[3]_AHCLKX/ PINCNTL14 USB1_DRVVBUS DSIS: PIN IPD – MCA[0]_AFSX L3 I/O McASP0 Transmit Frame Sync I/O DVDD PINCNTL18 AUD_CLKIN2/ AUD_CLKIN2, MCA[0]_AXR[9]/ MCA[1], MCA[4], MCA[2]_AHCLKX/ EDMA, TIMER2, IPD MCA[5]_AHCLKX/ H1 I/O GP0 DVDD EDMA_EVT2/ PINCNTL16 TIM3_IO/ DSIS: PIN GP0[9] MM: MUX1 MCB MCA[0]_AXR[9]/ IPD PINCNTL30 MCB_CLKX/ M6 I/O DVDD DSIS: PIN MCB_CLKR MM: MUX0 AUD_CLKIN1/ AUD_CLKIN1, MCA[0]_AXR[8]/ MCA[1], MCA[4], MCA[1]_AHCLKX/ EDMA, TIMER2, IPD MCA[4]_AHCLKX/ R5 I/O GP0 DVDD EDMA_EVT3/ PINCNTL15 McASP0 Transmit/Receive Data I/Os TIM2_IO/ DSIS: PIN GP0[8] MM: MUX1 MCB MCA[0]_AXR[8]/ IPD PINCNTL29 MCB_FSX/ L1 I/O DVDD DSIS: PIN MCB_FSR MM: MUX0 AUD_CLKIN0, AUD_CLKIN0/ MCA[0], MCA[3], MCA[0]_AXR[7]/ IPD USB1 MCA[0]_AHCLKX/ L5 I/O DVDD PINCNTL14 MCA[3]_AHCLKX/ DSIS: PIN USB1_DRVVBUS MM: MUX1 MCB MCA[0]_AXR[7]/ IPD PINCNTL28 L2 I/O MCB_DX DVDD DSIS: PIN MM: MUX0 (1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De- selected Input State (2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset. (3) Specifies the operating I/O supply voltage for each signal 98 Device Pins Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320DM8148 TMS320DM8147 |
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