Si4322

2

DETAILED DESCRIPTION

General

The

FSK transmitter. It covers the unlicensed frequency bands at 868

and 915 MHz. The device facilitates compliance with FCC and ETSI

requirements.

The programmable PLL synthesizer determines the operating

frequency, while preserving accuracy based on the on-chip crystal-

controlled reference oscillator. The PLL’s high resolution allows for

the use of multiple channels in any of the bands.

The receiver employs the Zero-IF approach with I/Q demodulation,

allowing the use of a minimal number of external components in a

typical application. The

band PLL synthesizer, an LNA with switchable gain, I/Q down

converter mixers, baseband filters and amplifiers, and an I/Q

demodulator followed by a data filter.

LNA

The LNA has 250 Ohm input impedance, which works well with the

recommended antennas. (See Application Notes available from

www.silabs.com/integration.)

If the RF input of the chip is connected to 50 Ohm devices, an

external matching circuit is required to provide the correct matching

and to minimize the noise figure of the receiver.

The LNA gain (and linearity) can be selected (0, –6, –12, –18 dB

relative to the highest gain) according to RF signal strength. This is

useful in an environment with strong interferers.

Baseband Filters

The receiver bandwidth is selectable by programming the bandwidth

(BW) of the baseband filters. This allows setting up the receiver

according to the characteristics of the signal to be received.

An appropriate bandwidth can be selected to accommodate various

FSK deviation, data rate, and crystal tolerance requirements. The

filter structure is a 7-th order Butterworth low-pass with 40 dB

suppression at 2*BW frequency. Offset cancellation is accomplished

by using a high-pass filter with a cut-off frequency below 15 kHz.

Data Filtering and Clock Recovery

The output data filtering can be completed by an external capacitor

or by using digital filtering according to the final application.

Analog operation:

Analog operation:

Analog operation:

Analog operation:

Analog operation: The filter is an RC type low-pass filter and a

Schmitt-trigger (St). The resistor (10k) and the St is integrated on

the chip. An (external) capacitor can be chosen according to the

actual bit-rate. In this mode the receiver can handle up to 256 kbps

data rate.

Digital operation:

Digital operation:

Digital operation:

Digital operation:

Digital operation: The data filter is a digital realization of an analog

RC filter followed by a comparator with hysteresis. In this mode there

is a clock recovery circuit (CR), which can provide synchronized clock

to the data. With this clock the received data can fill the RX Data

FIFO. The CR has three operation modes: fast, slow, and automatic.

In slow mode, its noise immunity is very high, but it has slower settling

time and requires more accurate data timing than in fast mode. In

automatic mode the CR automatically changes between fast and

slow modes. The CR starts in fast mode, then automatically switches

to slow mode after locking.

(Only the data filter and the clock recovery use the bit-rate clock.

Therefore, in analog mode, there is no need for setting the correct

bit-rate.)

Data Validity Blocks

RSSI

RSSI

RSSI

RSSI

RSSI

A digital RSSI output is provided to monitor the input signal level. It

goes high if the received signal strength exceeds a given

preprogrammed level. An analog RSSI signal is also available. The

RSSI settling time depends on the filter capacitor used.

P1

-65 dBm

1300 mV

P2

-65 dBm

1000 mV

P3

-100 dBm

600 mV

P4

-100 dBm

300 mV

Input Power [dBm]

RSSI

voltage

[V]

P4

P2

P1

P3

Voltage on ARRSI pin vs. Input RF power