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AD9248-40PCB 데이터시트(PDF) 10 Page - Analog Devices |
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AD9248-40PCB 데이터시트(HTML) 10 Page - Analog Devices |
10 / 23 page AD9248 Preliminary Technical Data Rev. PrE | Page 10 of 23 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 12 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 55 54 53 52 51 50 49 59 58 57 56 PIN 1 IDENTIFIER 64-LEAD LF-CSP AND TQFP TOP VIEW (Not to Scale) D4_A D3_A D2_A D1_A D0_A DRGND OTR_B D11_B D10_B D9_B D8_B AD9248 AGND AVDD REFT_A REFB_A VREF SENSE REFB_B AGND VIN– _B VIN+_B VIN+_A VIN – _A AVDD REFT_B D6_A D5_A AGND AGND DRVDD D13_B (MSB) D12_B Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin Number Mnemonic Description 2 VIN+_A Analog Input Pin (+) for Channel A 3 VIN–_A Analog Input Pin (- ) for Channel A 15 VIN+_B Analog Input Pin (+) for Channel B 14 VIN- _B Analog Input Pin (- ) for Channel B 6 REFT_A Differential Reference (+) for Channel A 7 REFB_A Differential Reference (- ) for Channel A 11 REFT_B Differential Reference (+) for Channel B 10 REFB_B Differential Reference (- ) for Channel B 8 VREF Voltage Reference Input/Output 9 SENSE Reference Mode Selection 18 CLK_B Clock Input Pin for Channel B 63 CLK_A Clock Input Pin for Channel A 19 DCS Enable Duty Cycle Stabilizer (DCS) Mode 20 DFS Data Output Format Select Bit (Low for Offset Binary, High for Twos Complement) 21 PDWN_B Power-Down Function Selection for Channel B (Active High) 60 PDWN_A Power-Down Function Selection for Channel A (Active High) 22 OEB_B Output Enable Bit for Channel B 59 OEB_A Output Enable Bit for Channel A (Low Setting Enables Channel A Output Data Bus) 42–51, 54- 57 D0_A (LSB)-D13_A (MSB) Channel A Data Output Bits 23–27, 30- 38 D0_B (LSB) -D13_B (MSB) Channel B Data Output Bits 39 OTR_B Out-of-Range Indicator for Channel B 58 OTR_A Out-of-Range Indicator for Channel A 62 SHARED_REF Shared Reference Control Bit (Low for Independent Reference Mode, High for Shared Reference Mode) |
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