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CAT25020P 데이터시트(PDF) 7 Page - Catalyst Semiconductor |
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CAT25020P 데이터시트(HTML) 7 Page - Catalyst Semiconductor |
7 / 11 page 7 CAT25010/20/40 Doc. No. 1006, Rev. L Figure 4. Read Instruction Timing Figure 5. RDSR Instruction Timing Note: Dashed Line= mode (1, 1) – –––– SK SI SO 0000001 1 BYTE ADDRESS* 0123456789 10 20 21 22 23 24 25 26 27 28 29 30 7 6 5 4 3 2 1 0 *Please check the instruction set table for address CS OPCODE DATA OUT MSB HIGH IMPEDANCE 0 1 2 345 67 8 10 911 12 13 14 SCK SI DATA OUT MSB HIGH IMPEDANCE OPCODE SO 7 6 5 4 3 2 1 0 CS 00 0 00 1 0 1 to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to 0000h allowing the read cycle to be continued indefinitely. The read operation is terminated by pulling the CS high. To read the status register, RDSR instruction should be sent. The contents of the status register are shifted out on the SO line. The status register may be read at any time even during a write cycle. Read sequece is illustrated in Figure 4. Reading status register is illustrated in Figure 5. WRITE Sequence The CAT25010/20/40 powers up in a Write Disable state. Prior to any write instructions, the WREN instruction must be sent to CAT25010/20/40. The device goes into Write enable state by pulling the CS low and then clocking the WREN instruction into CAT25010/20/40. The CS must be brought high after the WREN instruction to enable writes to the device. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the |
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