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932SQL456AKILF 데이터시트(PDF) 5 Page - Integrated Device Technology |
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932SQL456AKILF 데이터시트(HTML) 5 Page - Integrated Device Technology |
5 / 23 page REVISION B 09/29/15 5 LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 932SQL456 DATASHEET 64VFQFPN Pin Descriptions (cont.) PIN # PIN NAME TYPE DESCRIPTION 39 NS_SAS1_Z85C OUT Complementary clock of low-power push-pull differential non-spreading SAS output. Internally terminated to drive 85ohm transmission lines with no external components. 40 NS_SAS1_Z85T OUT True clock of low-power push-pull differential non-spreading SAS output. Internally terminated to drive 85ohm transmission lines with no external components. 41 AVDD_NS_SAS PWR 3.3V power for the non-spreading SAS/SRC PLL analog circuits. 42 GNDNS PWR Ground pin for non-spreading differential outputs and logic. 43 CPU0_Z85C OUT Complementary clock of low-power push-pull differential CPU output. Internally terminated to drive 85ohm transmission lines with no external components. 44 CPU0_Z85T OUT True clock of low-power push-pull differential CPU output. Internally terminated to drive 85ohm transmission lines with no external components. 45 CPU1_Z85C OUT Complementary clock of low-power push-pull differential CPU output. Internally terminated to drive 85ohm transmission lines with no external components. 46 CPU1_Z85T OUT True clock of low-power push-pull differential CPU output. Internally terminated to drive 85ohm transmission lines with no external components. 47 VDDCPU PWR 3.3V power for the CPU outputs and logic 48 GNDCPU PWR Ground pin for CPU outputs and logic. 49 CPU2_Z85C OUT Complementary clock of low-power push-pull differential CPU output. Internally terminated to drive 85ohm transmission lines with no external components. 50 CPU2_Z85T OUT True clock of low-power push-pull differential CPU output. Internally terminated to drive 85ohm transmission lines with no external components. 51 CPU3_Z85C OUT Complementary clock of low-power push-pull differential CPU output. Internally terminated to drive 85ohm transmission lines with no external components. 52 CPU3_Z85T OUT True clock of low-power push-pull differential CPU output. Internally terminated to drive 85ohm transmission lines with no external components. 53 VDDCPU PWR 3.3V power for the CPU outputs and logic 54 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant 55 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant 56 GND14 PWR Ground pin for 14MHz output and logic. 57 AVDD14 PWR Analog power pin for 14MHz PLL 58 VDD14 PWR Power pin for 14MHz output and logic 59 vREF14_2x/TEST_SELLV I/O 14.318 MHz reference clock capable of driving 2 loads/ TEST_SEL latched input to enable test mode. The TEST_SEL input is a low threshold input. See the Electrical Tables and the Test Clarification Table. This pin has a weak (~120Kohm) internal pull down. 60 GND14 PWR Ground pin for 14MHz output and logic. 61 GNDXTAL PWR Ground pin for Crystal Oscillator. 62 X1_25 IN Crystal input, Nominally 25.00MHz. 63 X2_25 OUT Crystal output, Nominally 25.00MHz. 64 VDDXTAL PWR 3.3V power for the crystal oscillator. 65 EPAD GND Epad should be connected to ground. |
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