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CS5372-BS 데이터시트(PDF) 11 Page - Cirrus Logic |
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CS5372-BS 데이터시트(HTML) 11 Page - Cirrus Logic |
11 / 22 page CS5371/CS5372 DS255PP2 11 4.4. Maximum Signal Levels The CS5371/CS5372 modulators are 4th order and are therefore conditionally stable, and may go into an oscillatory condition if the analog inputs over- range beyond full scale by more than 5%. If an un- stable condition is detected, the modulators col- lapse to a 1st order system until loop stability is achieved. During this time, the MFLAG pin tran- sitions from low to high signaling the CS5376 dig- ital filter to set an error bit in the digital output word. The analog input signal must be reduced to within the full scale range of the converter for at least 32 MCLK cycles for the modulators to recov- er from an unstable condition. 5. INPUT OFFSET The CS5371/CS5372 modulators are ∆−Σ type and so can produce ‘idle tones’ in the passband when the input signal is a steady state DC signal within about ±50 mV of the common mode input voltage. Idle tones result from patterns in the output bit- stream and appear in the measurement spectrum about -135 dB down from full scale. Idle tones can be eliminated by adding 100 mV or more of differential DC offset to the modulator in- puts. The added offset should be applied differen- tially to the inputs, common mode offsets do not affect idle tones. 5.1. Offset Enable - OFST If the analog inputs are within ±50 mV of the com- mon mode voltage when no signal is present, the OFST pin can be used to eliminate idle tones. When OFST=1, +100 mV of differential offset is added to the modulator analog inputs to push the idle tones out of the measurement bandwidth. Care should be taken that when OFST is active, offset voltages generated by external circuitry do not ne- gate the internally added offset. 5.2. Offset Drift Offset drift characteristics vary from part to part and with changes in the power supply voltages. If the CS5371/CS5372 is used in precision DC mea- surement applications where offset drift is to be minimized, the power supplies should be well reg- ulated. For the lowest offset drift, the CS5371/CS5372 modulators should operate with an MCLK of 2.048 MHz. The offset drift rate is inversely pro- portional to clock frequency, with slower modula- tor clock rates exhibiting more offset drift. Operating from an MCLK of 1.024 MHz results in twice the offset drift rate compared to an MCLK of 2.048 MHz. Because offset drift is not linear with temperature, an exact drift rate per °C cannot be specified. The CS5371/CS5372 modulators will exhibit approxi- mately 5 ppm/°C of offset drift operating with an MCLK of 2.048 MHz. 6. VOLTAGE REFERENCE INPUTS The CS5371/CS5372 modulators are designed to operate with a 2.5 V voltage reference applied across the VREF+ and VREF- pins to set the full scale signal range of the analog inputs. A 2.5 V voltage reference results in the highest dynamic range and best signal-to-noise performance, though smaller reference voltages may be used. When the CS5371/CS5372 modulators are operated with a 2.5 V reference, the analog inputs measure full scale signals of 5 volts peak-to-peak, or 2.5 volts differential. In a single supply power configuration the voltage reference output should be connected to the VREF+ pin with the VREF- pin connected to ground. In a dual supply power configuration the voltage reference should be powered from the VA+ and VA- supplies, with the modulator VREF+ pin connected to the voltage reference output and the |
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